Method of preventing silicide spiking

Details Method of preventing silicide spiking Method of preventing silicide spiking

2002-01-03

2003-03-25

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S655000, C438S656000, C438S657000, C438S663000

Reexamination Certificate

active

06537909

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of preventing silicide spiking, and more particularly, to a method of preventing the occurrence of silicide spiking to a gate of an embedded dynamic random access memory (EDRAM) cell.
2. Description of the prior Art
Dynamic random access memory (DRAM) is composed of a memory array region and a logic circuit region. With increasing integration of electrical circuit elements, the trend of manufacturing semiconductor integrated circuits is to integrate memory array region and high-speed logic circuit elements into a single chip to form an embedded memory. The embedded memory not only significantly reduces the circuit area but also greatly increases the signal processing speed.
In order to improve the electrical performance of the embedded memory, a silicide layer is often required in a gate structure to reduce contact resistance of the gate. However, during the formation of the gate, silicide spiking occurs. The silicide spiking is resulted from the solubility of metal such as titanium (Ti) or aluminum (Al) in silicon. Specifically, metal ions in the silicide layer frequently penetrate through the interface of the silicide layer and the polysilicon layer to diffuse into the polysilicon layer, forming silicide spiking to affect the electrical performance of the gate. Currently, a method to prevent silicide spiking is to form a barrier layer on the polysilicon layer prior to the deposition of the silicide layer. Thus, by using the barrier layer, metal ions are prevented from diffusing downward to induce silicide spiking.
Please refer to FIG.
1
and
FIG. 2
of schematic diagrams of fabricating a wire according to the prior art. As shown in
FIG. 1
, a silicon oxide layer
12
, a polysilicon layer
14
, a barrier layer
16
and a silicide layer
18
are formed, respectively, on a surface of a semiconductor substrate
10
. Normally, the barrier layer
16
is a silicon nitride layer and the silicide layer
18
is a titanium silicide (TiSi
2
) layer. A conventional method to form the barrier layer
16
is to use a physical vapor deposition (pVD) process, such as reactive sputtering method, with argon gas and nitrogen gas as reactive gases to bombard a metal target to release titanium atoms. The released titanium atoms thereafter react with nitrogen atoms that are ionized by the plasma, forming titanium nitride on the surface of the polysilicon layer
14
. However, the structure of the barrier layer
16
formed by reactive sputtering method is seldom tight enough to prevent metal ions in the silicide layer
18
from diffusing downward in a subsequent thermal process. Thus, a spike
19
of the silicide layer
18
is produced to intrude into the barrier layer
16
, and even into the polysilicon layer
14
.
Subsequently, as shown in
FIG. 2
, a photolithographic and etching process is performed. A photoresist layer (not shown) is coated on the surface of the semiconductor substrate
10
to define gate patterns in the photoresist layer. According to the patterns in the photoresist layer, portions of the silicide layer
18
, portions of the barrier layer
16
, portions of the polysilicon layer
14
and portions of the silicon oxide layer
12
are removed down to the surface of the silicon substrate
10
, thus forming a gate
20
. Finally, fabricating processes to form other electrical elements, such as source and drain, are performed to complete the MOS transistor of the EDRAM cell. The details of these processes are not the major concern and are thus omitted for simplicity of description.
As the physical vapor deposition of the prior art cannot provide a tight barrier layer
16
, the spike
19
occurs on the interface between the silicide layer
18
and the barrier layer
16
and induces leakage currents to affect the electrical performance. In addition, portions of the spike
19
penetrating through the barrier layer
16
also destroy stress properties of the whole barrier layer
16
, thus reducing the reliability of the gate
20
.
SUMMARY OF INVENTION
It is therefore an objective of the present invention to prevent the occurrence of a spike in a silicide layer as in the prior art.
It is another objective of the present invention to provide a method of improving a ring oscillator period of an EDRAM cell and increasing the reliability thereof.
According to the claimed invention, a polysilicon layer is formed on a semiconductor substrate followed by performing a collimator physical vapor deposition process to form a barrier layer on the polysilicon layer. A rapid thermal process (RTP) is then performed to tighten the structure of the barrier layer. Finally, a silicide layer is formed on the barrier layer.
It is an advantage of the present invention that the collimator is used as an assistant to form the barrier layer and the RTP process is performed to tighten the barrier layer's structure after the deposition of the barrier later. As a result, the silicide layer is prevented from occurring spiking, the contact resistance of the polysilicon layer is reduced, and the production reliability is improved. In addition, as the method of forming the barrier layer of the present invention is employed in an EDRAM cell, especially in a gate of a MOS transistor in the logic circuit region, an obvious decrease in a ring oscillator period of the logic circuit region is made as a result of decreasing the contact resistance of the gate. To be specific, the delay time of the logic circuit region is reduced as a result of decreasing the contact resistance of the gate, thus both the logical computation ability and the electrical performance are greatly improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF DRAWINGS
FIG.
1
and
FIG. 2
are schematic diagrams of fabricating a wire according to the prior art.
FIG.
3
and
FIG. 4
are schematic diagrams of fabricating a wire according to the present invention.


REFERENCES:
patent: 5604140 (1997-02-01), Byun
patent: 5608249 (1997-03-01), Gonzalez
patent: 5668394 (1997-09-01), Lur et al.
patent: 5695564 (1997-12-01), Imahashi
patent: 6217721 (2001-04-01), Xu et al.
patent: 6281052 (2001-08-01), Shinmura
patent: 6334411 (2002-02-01), Yamada et al.

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