Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-02-08
2001-06-05
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S697000, C438S700000, C438S704000, C438S706000, C438S723000
Reexamination Certificate
active
06242352
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor wafer, and more particularly, to a method of preventing micro-scratches on the surface of a semiconductor wafer during chemical mechanical polishing.
2. Description of the Prior Art
The CMP (chemical-mechanical polishing) process is a very commonly used semiconductor process. It is performed to planarize the surface of the semiconductor wafer by removing unwanted substance from it. The polish rate of the CMP process varies with the use of different polishing media and is therefore very difficult to control. This often leads to over-etching or under-etching. In a semiconductor wafer that has shallow trenchs, the CMP process is performed to remove only a portion of unwanted substance, and the remaining unwanted substance is removed by using a method with a more stable polish rate to prevent micro-scratches caused by over-etching.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional view of a prior art semiconductor wafer
10
before performing a CMP process. The semiconductor wafer
10
comprises a silicon substrate
12
,a pad oxide layer
14
composed of silicon oxide (SiO
x
) formed on the silicon substrate
12
, a second dielectric layer
16
composed of silicon nitride (Si
3
N
x
) deposited on the pad oxide layer
14
, a plurality of shallow trenches
18
positioned on the silicon substrate
12
for isolating components on the semiconductor wafer
10
, and a first dielectric layer
20
composed of silicon oxide (SiO
x
) positioned on the second dielectric layer
16
for filling the shallow trenches
18
.
Please refer to FIG.
2
.
FIG. 2
is a cross-sectional view of the semiconductor wafer
10
after performing the CMP process. When the CMP process is performed on the first dielectric layer
20
of the semiconductor wafer
10
, a predetermined thickness of the first dielectric layer
20
is removed to make the surface of the semiconductor wafer
10
approximately even. Then the remaining height of the first dielectric layer
20
is measured. If the remaining thickness is within a predetermined range, the remaining first dielectric layer
20
is removed horizontally by performing an etching back process. Please refer to FIG.
3
.
FIG. 3
is a cross-sectional view of the semiconductor wafer
10
after performing the etching back process. After performing the etching back process, a flat surface is formed by the second dielectric layer
16
and several shallow trenches
18
on the semiconductor wafer
10
.
Please refer to FIG.
4
.
FIG. 4
is a flowchart of a prior art etching method
22
. To accurately perform the etching back process, the predetermined range of remaining thickness of the first dielectric layer
20
is defined very small. Because the polishing rate of the CMP process is unstable, the remaining thickness of the first dielectric layer
20
frequently exceeds the predetermined range. If the remaining thickness of the first dielectric layer
20
exceeds the predetermined range, the etching back process cannot be performed, and the operators have to stop the process and perform special, time-consuming manipulations. The etching method
22
is very rigid and often interrupts the process thus increasing the workload of process engineers.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method to solve the above mentioned problem.
In a preferred embodiment, the present invention relates to a method for removing a first dielectric layer of a semiconductor wafer, the first dielectric layer being formed on the surface of a second dielectric layer of the semiconductor wafer, the method comprising:
performing a chemical mechanical polishing (CMP) process on the first dielectric layer to remove a predetermined thickness of the first dielectric layer;
measuring the remaining thickness of the first dielectric layer;
providing an etching table having a plurality of thickness ranges of the remaining first dielectric layer and corresponding etching back procedure or parameters of each of the thickness ranges; and
performing an etching back process to horizontally remove the remaining first dielectric layer according to the etching back procedure or parameters of the thickness range corresponding to the measured thickness of the remaining first dielectric layer.
It is an advantage of the present invention that the etching back process is performed according to the thickness of the remaining first dielectric layer. This means the thickness of the remaining first dielectric layer can have a more flexible range, and thus micro-scratches caused by over-etching can be avoided.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5196353 (1993-03-01), Sandhu et al.
patent: 5298110 (1994-03-01), Schoenborn et al.
patent: 5429711 (1995-07-01), Watanabe et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5494857 (1996-02-01), Cooperman et al.
patent: 5663107 (1997-09-01), Peschke et al.
patent: 5668063 (1997-09-01), Fry et al.
patent: 5702977 (1997-12-01), Jang et al.
Chen Chien-Hung
Lu Water
Wu Juan-Yuan
Hsu Winston
Tran Binh X.
United Microelectronics Corp.
Utech Benjamin L.
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