Method of preventing cache corruption during microprocessor pipe

Details Method of preventing cache corruption during microprocessor pipe Method of preventing cache corruption during microprocessor pipe

1995-12-04

1998-07-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711169, G06F 1216

Patent

active

057819254

ABSTRACT:
In a microcomputer system implementing cache memory, the microprocessor can execute back-to-back pipelined burst operations without corrupting the internal address of the cache memory. The address strobe from the processor is blocked by the cache memory controller, allowing a burst operation to complete from or to the cache memories before the second address is strobed into the cache.

REFERENCES:
patent: 5210845 (1993-05-01), Crawford, et al.
patent: 5440751 (1995-08-01), Santeler et al.
patent: 5488709 (1996-01-01), Chan
patent: 5559993 (1996-09-01), Elliott et al.
patent: 5603007 (1997-02-01), Yazdy et al.
Motorola, Fast Static RAM Component and Module Data, Rev. 3, .COPYRGT.Motorola, Inc. 1995.

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