Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
2001-05-17
2003-10-21
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S916000
Reexamination Certificate
active
06635556
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to electronic devices and, more particularly, to methods of reducing or eliminating the effects of autodoping in chemical vapor deposition (hereinafter CVD) processes.
BACKGROUND OF THE INVENTION
Many steps in integrated circuit (IC) manufacture require the deposition of thin films of silicon. One method of depositing silicon in thin film form is by low pressure chemical vapor deposition (hereinafter LPCVD). Substrate wafers are heated in a pressure vessel to between 450 and 650° C. while atmospheric gases are pumped out. When the pressure in the vessel generally reaches between 200-600 mTorr and the wafers have reached high temperature, a silicon containing gas such as silane (SiH
4
) is flowed into the chamber, resulting in silicon deposition. Excellent control of the thickness of the film, thickness uniformity across a wafer, and step coverage (i.e., ability to cover a wafer surface with varied topography) is achieved by adjusting the temperature, pressure, and gas flow in the pressure vessel.
However, many steps in integrated circuit manufacture not only require the deposition of thin films of silicon, but also require that the thin film be doped to make it conductive. Doping describes intentionally contaminating the silicon with specific foreign atoms, such as boron or phosphorus. The most common method of doping silicon is by ion implantation. Ion implantation is a process by which foreign atoms are ionized, accelerated by electromagnetic fields, and directed to impact (“implant”) into a target substrate such as silicon. Ion implantation requires expensive equipment and does not allow for good control over the concentration depth profile of the dopant.
Another method of doping silicon thin films is to co-deposit dopant atoms while depositing silicon atoms. Precursor gases such as boron trichloride (BCl
3
) or phosphine (PH
3
) are admitted simultaneously with silane (SiH
4
) resulting in boron or phosphorus doped silicon films. This process is generally known as “in-situ” doping. In-situ doping allows for better control of the dopant depth profile concentration in the silicon film relative to ion implantation. Cost is also reduced as silicon film deposition and doping is done using the same furnace.
However, one major drawback of in-situ doping is the potential for autodoping. Autodoping is the unintentional doping of wafers in a vessel caused by the outgassing of dopant atoms in the silicon films from the previous deposition. When silicon wafers are deposited in an LPCVD method, the vessel and everything inside it (including any dummy wafers used for maintaining consistent deposition on product wafers) are all deposited with silicon film and, if any is present, dopant material. The silicon deposition is ubiquitous and indiscriminate on all heated surfaces in the pressure vessel.
Several prior art methods attempt to reduce or eliminate the effects of autodoping. One such method is to “wet” clean all the components of the LPCVD furnace. This requires shutting down the LPCVD furnace, removing any product wafers and using a chemical bath to etch away the doped layers formed on the LPCVD furnace components. This process is sometimes repeated after every product wafer deposition. This method is highly disadvantageous because LPCVD furnaces are notorious for their large overhead times. Overhead time is the time spent by the LPCVD furnace which is not dedicated strictly to product wafer depositions and includes the time to pump down the pressure vessel to low pressures, the time for the wafers to achieve a uniform process temperature, the time to cool down the wafers before they can be placed in plastic cassettes, etc. In some cases, the overhead time on LPCVD deposition sequences is on the order of four or more hours and is, therefore, nontrivial.
A second method is to “dry” clean all the components of the LPCVD furnace. This method involves once again effectively shutting down the LPCVD furnace, removing any product wafers and then pumping gaseous cleaning agents into the LPCVD furnace to etch away the doped layers formed therein. This process is also sometimes repeated after every product wafer deposition. This method also suffers from the above-discussed disadvantageously large overhead times because the LPCVD furnace must be effectively shut down (e.g., placed in a nonproductive operational state) to be cleaned and then restarted for the next product wafer deposition.
A third method is to run a separate and distinct undoped deposition process that is unrelated to the product wafer deposition process. This method requires removal of the product wafers from the furnace and then running a separate and distinct undoped deposition process to coat all of the surfaces of the LPCVD furnace components (and, if any, dummy wafers). This process-is also sometimes repeated after every product wafer deposition. Since the product wafers are not in the furnace during this deposition, large overhead times as discussed above are once again encountered because the LPCVD furnace must be effectively placed in nonproductive operation and restarted multiple times before the product wafer depositions can be once again formed.
Hence, a method of preventing autodoping that does not suffer from the aforementioned disadvantages is highly desirable.
SUMMARY OF THE INVENTION
The present invention employs very thin “capping” layers of undoped silicon that are deposited on top of the doped silicon layers of product wafers and/or dummy wafers to prevent outgassing of the dopants underneath the cap. In this regard, while the undoped capping layers may have some dopant in them due to out-gassing and diffusion from the doped layer below and the pressure vessel, the amount of dopant present is so low that the next product wafer deposition of doped silicon is not subject to autodoping by the previous doped silicon deposition.
According to one embodiment of the present invention, a continuous method of making a silicon-based electronic device is provided. The method includes, for example, the steps of forming a doped silicon layer on a surface of a substrate material and forming an undoped silicon capping layer on the doped silicon layer. A second doped silicon layer may be formed on the undoped silicon layer followed by another doped silicon capping layer, and so, on. In this manner, the undoped silicon capping layers prevent autodoping from the doped silicon layers beneath. The entire method is performed via a continuous in-situ process without having the LPCVD furnace in any nonproductive operational states between depositions.
For example, for a 1000 Å phosphorus-doped (ntype) silicon layer, an undoped silicon capping layer having a thickness of approximately 200 Å or greater is sufficient to reduce the effects of autodoping to most preferably a substantially background level. Also, for a 1000 Å boron-doped (p-type) silicon layer, an undoped silicon capping layer having a thickness of approximately 300 Å or greater is sufficient to reduce the effects of autodoping to most preferably a substantially background level.
Therefore, it is an advantage of the present invention to provide a continuous process for forming electronic devices that does not suffer from the drawbacks associated with autodoping.
It is yet another advantage of the present invention to provide a method of reducing autodoping wherein the capping layer can be used for subsequent processing such as, for example, the formation of wires or use during chemo-mechanical polishing (CMP).
It is still further an advantage of the present invention to provide a method reducing autodoping to substantially background concentrations.
It is still further an advantage of the present invention to provide a method of fabricating electronic devices with abrupt n and p-type interfaces.
REFERENCES:
patent: 3716422 (1973-02-01), Ing et al.
patent: 3775197 (1973-11-01), Sahagun
patent: 4662956 (1987-05-01), Roth et al.
patent: 4704624 (1987-11-01), Yamazaki et al.
patent: 4894349 (19
Cleeves James M.
Herner Scott B.
Knall Johan
Calfee Halter & Griswold
Matrix Semiconductor Inc.
Pejic Nenad
Squyers Pamela J.
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