Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2001-06-29
2004-03-23
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S777000, C257S778000, C257S780000, C257S783000, C257S785000, C438S106000, C438S111000, C438S118000, C438S119000, C438S122000, C438S123000
Reexamination Certificate
active
06710462
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor device packaging, and more particularly, to curing adhesive material affixing a semiconductor die in a device package.
BACKGROUND OF THE INVENTION
Integrated circuit devices are typically fabricated on thin wafers of silicon. Several die are produced on each wafer, with each die representing a single integrated circuit device. Each integrated circuit device on a wafer is tested for gross functionality, and sorted according to whether the device passes or fails the gross functionality test. After being sorted according to gross functionality, the wafers are cut using a wafer saw, and the individual die are singulated. The die having devices determined to be non-functional are scrapped. The die having functional devices are packaged and further tested to ensure that each packaged device satisfies a minimum level of performance. Typically, the functional devices are permanently packaged by encapsulating the die in a plastic package. Packaging of the functional devices facilitates handling of the devices and also protects the die from damage during the manufacture of modules using the packaged devices.
There are several conventional structures and methods for packaging singulated die. For example, more common package types include small outline j-bend (SOJ) packages, thin small outline packages (TSOP), and zigzag in-line packages (ZIP). The finished packaged devices are often mounted onto a substrate as part of a module. Singulated die are packaged in the aforementioned package types typically by attaching the die to a lead frame paddle and electrically coupling exposed bond pads of the die to metal leads. The lead frame, die, and a portion of the metal leads are subsequently encapsulated by a plastic resin to protect the integrated circuit from damage. The encapsulated device is then trimmed from the lead frame and the metal leads formed to the correct bend.
An alternative lead frame structure, known as lead on chip (LOC) has been employed instead of the package structure having a lead frame paddle. In an LOC structure, individual metal leads are typically attached to the surface of the die using double-sided adhesive tape having a polyimide base coated on both sides with adhesive material. The metal leads and die are then heated to cure the adhesive material. The bond pads of the semiconductor die are subsequently wire bonded to a respective metal lead. The LOC lead frame and die are then encapsulated in a plastic resin, then followed by a trim and form process. The LOC structure and packaging process are described in U. S. Pat. No. 4,862,245 to Pashby et al., issued Aug. 29, 1989, and U. S. Pat. No. 4,916,519 to Ward, issued Apr. 10, 1990, which are incorporated herein by reference.
Recently, semiconductor manufacturers have developed a package structure where unpackaged die are mounted directly onto a substrate, for example, a printed circuit board, thus allowing modules to be designed with increased device density. The devices are mounted onto the substrate and are electrically coupled by wire bonding the bond pads of the die to conductive traces formed on the surface of the substrate. The die are typically attached to the substrate by using strips of single or double-sided adhesive tape that are sandwiched between the substrate and the die. Following attachment, the substrate and die are heated to cure the adhesive in order to firmly fix the die.
As described above, many of the current methods of packaging semiconductor die involved attaching the die to a lead frame or a substrate using a single or double-sided adhesive tape. As mentioned previously, the adhesive tape is typically formed from a heat resistant polyimide base coated on both sides with adhesive material. In order to firmly attach the semiconductor die, the adhesive is cured by heating. A typical example of the temperature profile of the curing process is: 5° C./min. ramp from room temperature to 110° C.; one hour soak; 5° C./min. ramp from 110° C. to 165° C.; one hour soak; −5° C./min ramp from 165° C. back down to room temperature.
A problem with the conventional temperature cure processes is that it is time-consuming, and often times, voids are created in the die attach bondline. The die attach bondline is defined as the interface between the surface of the die and the adhesive. In the ideal case, there would be no voids in the adhesive, so that the entire area of the die in contact with the adhesive would be flush with the adhesive. However, voids are formed at the interface between die and adhesive during the temperature cure process for various reasons. For example, voids are often formed during the cure step because moisture absorbed by the polyimide base evaporates during the relatively high temperature cure process. The evaporated moisture causes bubbles to form in the adhesive. Consequently, after the adhesive has been fully cured, voids resulting from the bubbles being trapped at the interface between the die surface and the adhesive material remain in the die attached bondline.
Voids in the die attach bondline may be further caused by incomplete wetting spots in the adhesive prior to the cure process, residual solvents out-gassing from the adhesive during the temperature cure, or by unreacted organic material in the adhesive.
The voids generated during the relatively high temperature cure step degrade the reliability of the resulting semiconductor device package. One potential failure mechanism results when gases trapped in the voids formed along the die attach bondline quickly expand when subjected to a thermal reflow process during the mounting of the packaged device onto a printed circuit board. In the worst case, the rapid expansion of the gases within the voids will cause the semiconductor die to delaminate from the adhesive. Consequently, where the semiconductor die is encapsulated in a plastic resin, separation of the die from the adhesive may cause the plastic package to crack, compromising the integrity of the integrated circuit device. Therefore, there is a need for a method of attaching a die to a substrate where the formation of voids at the interface between the adhesive and the die surface is reduced.
SUMMARY OF THE INVENTION
The present invention is directed to a method of curing adhesives of a die attach material to reduce the formation of voids at the resulting bondline. The resulting bondline, defined by the interface between the adhesive and the surface of a die being attached, will have less voids than with the conventional curing process. The method includes applying a relatively high pressure, in addition to a relatively high temperature, to cure the adhesive material.
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Dorsey & Whitney LLP
Fahmy Wael
Louie Wai-Sing
Micro)n Technology, Inc.
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