Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-01
2006-08-01
Zhen, Wei (Department: 2191)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C717S127000, C703S014000
Reexamination Certificate
active
07086017
ABSTRACT:
A method of post-implementation simulation of a hardware description language (HDL) net list file, that does not match a HDL design file from which it was synthesized, comprises the steps of: creating a remap file which translates ports between the HDL net list file and the HDL design file; and simulating the HDL net list file utilizing the remap file and a (HDL) test bench file created for pre-implementation simulation of the HDL design file. The method may be executed in an integrated software environment or a batch software environment.
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Brush Robert
Steelman Mary
Xilinx , Inc.
Zhen Wei
Zitelli William L.
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