Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-03-30
2003-12-30
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S723000
Reexamination Certificate
active
06670278
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an improved process of plasma etching dielectric materials such as silicon carbide.
BACKGROUND OF THE INVENTION
In the discussion of the state of the art that follows, reference is made to certain structures and/or methods. However, the following references should not be construed as an admission that these structures and/or methods constitute prior art. Applicant expressly reserves the right to demonstrate that such structures and/or methods do not qualify as prior art against the present invention.
Semiconductor materials may be manufactured into specific electronic devices, such as transistors, diodes, capacitors and the like, by the selective build up and removal of layers of materials. In the fabrication of integrated circuits, the continuing increase in the number of devices on a chip and the accompanying decrease in the minimum feature sizes have placed increasingly difficult demands upon many of the fabrication steps used in integrated circuit fabrication including depositing layers of different materials onto sometimes difficult topologies and the removal of material and formation of features within those layers.
Etching is one technique for removing layers of semiconductor or other materials from a given substrate and producing features on integrated circuits. During an etching process material is removed by interaction with another material, generally referred to as the etchant. Etching techniques fall into two broad categories: wet etching which generally refers to techniques which take place in solutions or molten salts or other liquid materials; and dry etching which generally refers to the use of gases or plasmas to perform the removal.
Dry etching techniques are of particular interest in producing electronic devices because they generally exhibit better resolution and improved dimensional and shape control capabilities than do the various methods of wet etching. Accordingly, dry etching is favorably utilized where superior pattern control and delineation are required, such as the processing of semiconductor wafers to form large scale integrated devices and integrated circuits.
One important factor associated with etching is etch selectivity. Etch selectivity refers to the ratio of etch rates of two different materials on a workpiece undergoing etching in the plasma reactor. In one scenario, it is desired that a first material on a workpiece be etched much faster than a second material. This is the scenario, for example, when employing masking techniques. Etch processes advantageously employing selectivity ratios may produce high aspect ratio features, defined as the ratio of the depth to the width of a feature, and contribute to high density features.
A second important factor associated with etching is anisotropy. Anisotropy refers to the directional dependence of the etch rate. Based on crystallographic preferences or etching conditions, an etch may occur in one direction of a material at a different rate than in a second direction. However, anisotropy should not be achieved by operating the plasma reactor in a pure sputtering mode in which the plasma ejects particles toward the wafer with sufficiently high energy that they sputter the material. Sputtering is generally non-selective, and high-energy sputtering may degrade semiconducting material exposed at the bottom of etched features. Etch processes advantageously employing anisotropy may produce vertical side walls in features and contribute to high density features.
A plasma reactor may be employed to perform various processes on a semiconductor wafer in microelectronic fabrication including dry etching. A wafer is placed inside a vacuum chamber of the reactor and process gases, including etchant gases, are introduced into the chamber. The gases are energized to ignite and maintain a plasma. Depending upon the composition of the gases from which the plasma is formed, the plasma may be employed to etch a particular material from the wafer or may be employed to deposit a thin film layer of material onto the wafer.
Selective etching processes have also been developed which depend more upon chemical effects. These processes are often described as reactive ion etching (RIE). A sufficiently high degree of selectivity allows new structures to be fabricated without the need for precise lithography for each level.
The manufacture of multilayer structures typically involves patterned etching of areas of the semiconductor surface that are covered by a photoresist protective material. Metallization patterns on integrated circuits can be formed by depositing a dielectric layer, patterning the dielectric layer to form a groove or trench, and depositing a metal layer that fills the trench in the dielectric layer. Any excess metal on the surface of the substrate is typically removed using either chemical-mechanical polishing (CMP) or an etch-back process. This process, called the “damascene process,” can be used to form conductors in-laid in a dielectric layer.
One method to pattern a dielectric layer is photolithography combined with reactive ion etching (RIE). In this process, a semiconductor wafer is patterned with a photoresist mask and is positioned in a reaction chamber. Etchant gases are fed into the chamber and dissociated in a radio frequency (RF) field so that ions contained in the etchant gases are accelerated to the wafer surface. The accelerated ions combine chemically with unmasked material on the wafer surface. As a result, volatile etch product is produced and is incorporated into the plasma. The concentration of the volatile etch product can be monitored in order to determine the end-point of the RIE process, i.e., when the chemical reaction has removed the desired level of material from the wafer surface. During the RIE process, a single layer or multiple layers of material or film may be removed. These materials may include, for example, silicon nitride (Si
3
N
4
), PSG, silicon dioxide (SiO
2
) and poly-silicon (PSi).
Multi-level structures containing vias and trenches can be formed by successive application of either a single-damascene or a dual-damascene process, or a combination of both types of processes. For example, in any level having a trench, a via could also be formed (either before or after formation of the trench) resulting in a dual-damascene recess. This recess is then typically lined with a liner (which functions as a diffusion barrier for the conductive material) and then filled with a conductive material.
In a typical dual damascene process, an etch stop can be used to facilitate formation of vias and trenches in an upper layer of the damascene structure. See, for example, U.S. Pat. No. 6,153,935. The etch-stop is typically a thin (about 20 to about 50 nm thick) layer of a silicon-based compound such as silicon nitride or silicon carbide. The etch-stop can be blanket-deposited by any process known in the art for depositing thin dielectric layers, such as CVD, evaporation, sputtering, etc. When a via is formed above the etch-stop in the formation of multi-level structures, the etch-stop is used to stop the first etch through the dielectric material above the etch-stop. A second, shorter etch using a different reactive gas mixture is then used to open the etch-stop layer to expose underlying layers.
Due to the small line widths of modern integrated circuits, it is becoming increasingly desirable to maintain vertical or near vertical sidewall profiles during etching. Thus, when etching through the etch stop layer, the etching of other layers of the multi-layer substrate such as dielectric materials which are exposed to the etching plasma should be minimized. Further, to maintain the flatness of the bottom of the opening, any over-etching of the dielectric material underlying the etch stop layer should also be minimized.
The development of new low-k dielectric materials (k<4) for use in damascene structures has created new challenges for etching vias and trenches. Many of these low-k materials, particularly the polymeric low-k ma
Bowers James
Goss Michael
Li Si Yi
Pirkle David R.
Reza Sadjadi S. M.
Burns Doane , Swecker, Mathis LLP
Chen Kin-Chan
Lam Research Corporation
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