Method of planarizing dielectric layer

Details Method of planarizing dielectric layer Method of planarizing dielectric layer

1998-04-27

2001-08-21

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S698000, C438S624000, C438S626000, C438S631000, C438S632000, C438S958000

Reexamination Certificate

active

06277754

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No.87103550, filed Mar. 11, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing semiconductors. More particularly, the present invention relates to a method of planarizing a borophosphosilicate glass (BPSG) dielectric layer.
2. Description of Related Art
Planarization is one of the most important steps in semiconductor fabrication. When the line width of semiconductors decreases to 2.0 &mgr;m or lower, difference in height levels across a wafer surface due to device miniaturization is going to increase. To ensure proper pattern transfer of conductive lines so that subsequent metallization operations can be performed without much interference, topographical variation across wafer surface must be dealt with by planarization. At present, the question of how to form a good planar surface on a wafer is still a major challenge for VLSI manufacturing engineers.
Borophosphosilicate glass (BPSG) is a dielectric material commonly used for planarizing a wafer surface before metallization. The composition of BPSG includes boron, phosphorus and silicon dioxide. BPSG is formed over a silicon wafer by the introduction of gases that contain boron and phosphorus while silicon dioxide is deposited. In general, BPSG contains about 1 to 4% boron by weight and about 4 to 6% phosphorus by weight. With this percentage of boron and phosphorus in the BPSG, the glass transition temperature necessary for thermal flow can be lowered to about 950° C., and sometimes can be below 850° C. In addition, the BPSG is able to absorb moisture from the air.
FIGS. 1A through 1D
are cross-sectional views showing the progression of manufacturing steps for the purpose of using BPSG as an inter-layer dielectric (ILD) in integrated circuit fabrication according to a conventional method. First, as shown in
FIG. 1A
, a substrate
100
is provided. Then, conductive lines or a MOS transistor having a gate
105
is formed on the substrate
100
, and source/drain regions
106
and device isolation regions
102
are formed in the substrate
100
. Next, an atmospheric pressure chemical vapor deposition (APCVD) method is used to form a borophosphosilicate glass (BPSG) layer
110
over the substrate
100
structure.
Next, as shown in
FIG. 1B
, the BPSG layer
110
on the wafer surface is heated to about 850° C. to perform a thermal flow operation. The thermal flow operation is able to smooth the top surface of the borophosphosilicate glass layer
110
a
a bit further. Moreover, the boron and phosphorus dopants inside the BPSG material can be more uniformly distributed by this operation.
Next, as shown in
FIG. 1C
, an etching back operation is carried out to remove a portion of the borophosphosilicate glass layer
110
a
so that a much more planar borophosphosilicate glass layer
110
b
is obtained. Next, using conventional photolithographic and etching techniques, the BPSG layer
110
b
is patterned to form a contact opening
112
exposing one of the source/drain regions
106
.
Next, as shown in
FIG. 1D
, an RCA cleaning solution is used to remove any residual photoresist or particles left after patterning the BPSG layer
110
b
. Subsequently, a pre-metal etching (PME) operation, normally a wet etching operation, is conducted to remove any native oxide on the exposed source/drain region
106
. Finally, a metallic layer
114
is formed over the substrate
100
, filling the contact opening
112
and making electrical contact with the source/drain region
106
.
As the level of integration, for integrated circuits increases, the dimensions of each device become smaller. Consequently, the thermal budget of each thermal operation must be reduced correspondingly. To reduce thermal budget, rapid thermal process (RTP) are often used in the aforementioned thermal flow process. Although RTP is capable of planarizing a BPSG layer, it is incapable of uniformly distributing boron and phosphorus dopants inside the BPSG layer. An increase in boron or phosphorus concentration in any part of a borophosphosilicate glass layer is able to increase the wet etching rate of silicon oxide at that point. Therefore, uneven distribution of boron or phosphorus dopants inside a borophosphosilicate glass layer will result in the formation of pits after a PME or cleaning with RCA solution, such as the region
120
as shown in FIG.
1
D. The formation of pits may cause severe problems in subsequent processing operations, and may lead to a change in electrical properties. Alternatively, the percentages of dopants in a BPSG layer can be purposely reduced so that less pits are formed. However, dopants reduction will increase the glass transition temperature of the borophosphosilicate glass layer, thus increasing thermal budget and thus compromising the ultimate planarity of the layer.
In light of the foregoing, there is a need to provide an improved method of planarizing the dielectric layer.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of planarization using a borophosphosilicate glass (BPSG) dielectric layer. The method is capable of preventing the formation of pits on a BPSG surface in pre-metal etching, but does not necessitate a reduction in the percentages of dopants inside the BPSG layer.
In another aspect, this invention provides a method of planarization using a borophosphosilicate glass (BPSG) dielectric layer. The method utilizes a rapid thermal process to generate the necessary heat for thermal flow of a borophosphosilicate glass layer, thereby reducing the overall thermal budget.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of planarization using a borophosphosilicate glass (BPSG) dielectric layer. The method comprises the steps of providing a substrate having structures already formed thereon, and then forming a borophosphosilicate glass layer over the substrate. Next, a rapid, thermal process is applied to heat the borophosphosilicate layer and cause a thermal flow, and then the borophosphosilicate layer is etched back so that a planar surface is obtained. Finally, a passivation layer is formed over the borophosphosilicate glass layer to prevent the formation of pits in subsequent pre-metal wet etching operation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5217566 (1993-06-01), Pasch et al.
patent: 5656556 (1997-08-01), Yang
patent: 5733818 (1998-03-01), Goto
patent: 5913131 (1999-06-01), Hossain et al.
patent: 5915175 (1999-06-01), Wise
patent: 5924007 (1999-06-01), Liang et al.

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