Method of planarizing a semiconductor topography using multiple

Details Method of planarizing a semiconductor topography using multiple Method of planarizing a semiconductor topography using multiple

1996-12-18

1999-10-19

Breneman, Bruce

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 38, 216 89, H01L 21302

Patent

active

059688432

ABSTRACT:
An improved method for planarizing an interlevel dielectric comprising two chemical mechanical polish steps. After an interlevel dielectric containing a topographical valley between a pair of topographical peaks is formed, the dielectric is chemically-mechanically polished in a first polish step at a first force using a first polish pad having a first rigidity to round the sharp dielectric corners or edges that exist at the transition between the peaks and valleys. After the first polish step has rounded the edges, a second polish step is performed with a second polish pad of second rigidity. The second polish pad is more rigid than the first polish pad and the second force is greater than the first. The second polish steps uses a high viscosity slurry to reduce slurry turnover in the regions proximate to the dielectric valleys thereby reducing the chemical etching in the valleys and improving the planarization efficiency.

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