Method of planarization

Details Method of planarization Method of planarization

1999-02-09

2001-08-21

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S694000, C438S697000

Reexamination Certificate

active

06277751

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of planarization. More particularly, the present invention relates to a method including the step of forming a spin-on-glass (SOG) layer over a semiconductor wafer prior to performing a chemical-mechanical polishing process, so that a smooth polished wafer surface is obtained.
2. Description of Related Art
In the fabrication of VLSI or ULSI circuits, all the devices, metallic interconnects or isolating trench structures on a semiconductor wafer must be carefully laid out so that the level of device integration and operating speed are optimized. However, these devices and structures are likely to be distributed non-uniformly above the semiconductor wafer. Consequently, a portion of the wafer surface will be densely packed while some other areas may have very few devices or isolating structures. Furthermore, all these devices and structures have different thicknesses. Hence, the wafer is likely to have a highly undulating cross-sectional profile. To facilitate the next processing process, the semiconductor wafer is usually planarized.
At present, the most commonly used method of planarizing a semiconductor wafer is the chemical-mechanical polishing (CMP) method. In a CMP process, chemical agents in the form of slurry are delivered to a rotating polishing table with a polishing pad on top. With the back of a wafer grasped by a handle, a global polishing of the wafer is carried out by pressing the front surface against the polishing pad though the handle. Since the polishing pad is made from a soft, flannel-like material, the pad is able to follow the varying contour of the wafer surface.
Because devices and structures are not evenly distributed on the surface of the semiconductor wafer, some areas are densely packed while other areas are loosely packed. Therefore, when an insulation layer is deposited over the semiconductor wafer, the insulating material will accumulate to a higher level in the densely packed areas than in the loosely packed areas. Subsequently, if a chemical-mechanical polishing process is carried out to planarize the wafer surface, recess cavities can easily form in the loosely packed device areas. Hence, a completely planarized semiconductor wafer surface is difficult to obtain.
FIGS. 1A through 1C
are schematic, cross-sectional views showing the progression of steps according to a conventional method of planarizing an insulation layer above a semiconductor wafer.
First, as shown in
FIG. 1A
, a semiconductor wafer
100
having a densely packed device region
108
and a loosely packed device region
110
thereon is provided. Next, an insulation layer
102
is formed over the substrate
100
in both regions
108
and
110
. The insulation layer can be formed by performing a chemical vapor deposition (CVD) process. The insulating material of the insulation layer
102
accumulates to a higher level in the densely packed device region
108
than in the loosely packed device region
110
. Hence, the upper surface of the insulation layer
102
has a highly undulating profile.
Next, as shown in
FIG. 1B
, a chemical-mechanical polishing (CMP) process is carried out to planarize the semiconductor wafer
100
. Due to the relative softness of the polishing pad
104
, the polishing pad
104
is able to contact the upper surface of the insulation layer
102
in the loosely packed region
110
more closely than the densely packed region
108
.
Thereafter, as shown in
FIG. 1C
, a recess cavity
106
is formed in the loosely packed device region
110
so that a not-so-planar insulating layer
102
results. Consequently, when material is deposited over the wafer, thickness tends to vary across the surface. Additionally, when the wafer is subsequently etched, depth of etching will tends to vary across the surface, too. Hence, more defects accumulate on the wafer and failure rate of the devices within the wafer is higher.
In light of the foregoing, there is a need to provide an improve method for planarizing a semiconductor wafer.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for planarizing a semiconductor wafer by preventing the formation of recess cavities above the loosely packed device areas of an insulation layer after performing a chemical-mechanical polishing process.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for planarizing a semiconductor wafer to prevent the formation of recess cavity in loosely packed device areas above an insulation layer. An insulation layer over a semiconductor wafer having a pre-defined upper profile is formed over a substrate. The upper profile of the semiconductor wafer is formed due to the formation of semiconductor devices, metallic interconnects, and trench structures above the substrate. Furthermore, the profile can be further divided into densely packed and loosely packed device regions. The insulation layer accumulates to a higher level in the densely packed region than in the loosely packed region. A spin-on-glass (SOG) layer is spin-coated over the insulation layer. A baking process is carried out to remove volatile organic solvent inside the SOG layer. A chemical-mechanical polishing process is conducted to planarize the wafer. The entire SOG layer is removed, retaining only an insulation layer polished to the expected thickness.
One major aspect of this invention is the coating of a spin-on-glass layer over the insulation layer prior to the carrying out of a planarization process. Spin-on-glass is highly flowable, and hence is able to form a very smooth planar surface. After the spin-on-glass material is baked, the spin-on-glass layer is planarized by performing a chemical-mechanical polishing process. The problem of having too many recess cavities in the loosely packed device region above the insulation layer is avoided.
Another aspect of this invention is that the curing process for solidifying the spin-on-glass layer is omitted. In other words, only the spin-coating process for forming a spin-on-glass layer over the insulation layer and its subsequent baking process are performed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5302233 (1994-04-01), Kim et al.
patent: 5312512 (1994-05-01), Allman et al.
patent: 5503882 (1996-08-01), Dawson
patent: 5532191 (1996-07-01), Nakano et al.
patent: 5654216 (1997-08-01), Adrian
patent: 5674784 (1997-10-01), Jang et al.
patent: 5679610 (1997-10-01), Matsuda et al.
patent: 5705028 (1998-01-01), Matsumoto
patent: 5705435 (1998-01-01), Chen

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