Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-25
2011-01-25
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07877709
ABSTRACT:
A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division boundary, confirming whether the shield subject wire exists around the division boundary in the second area when the division boundary is not laid on top of the wire track, and determining whether to place the shield wire on a wire track being adjacent to division boundary in the first area based on the confirming.
REFERENCES:
patent: 6951007 (2005-09-01), Kaida
patent: 2004/0031010 (2004-02-01), Kaida
patent: 2006/0190902 (2006-08-01), Shirai
patent: 2974398 (1999-09-01), None
Chiang Jack
Parihar Suchin
Renesas Electronics Corporation
Sughrue & Mion, PLLC
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