Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-08
2003-01-21
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06510542
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method for repeater insertion in electrical circuitry at the micro-circuitry level.
BACKGROUND ART
In today's design of VLSI high speed circuits, frequency has a major impact on the number of repeater cells that need to be inserted. A microprocessor operating at less than 200 MHz might require several hundred repeater cells, whereas one operating at greater than 500 MHz may require a number in the thousands.
In a high performance VLSI design, signal propagation over on-chip metal interconnect is significant due to RC delay. In general, the interconnect delay increases with the square of the length of the line. Delay can be reduced by inserting a repeater cell such as an inverting or non-inverting buffer.
Prior art methods of repeater insertion determined buffer placement based on maintaining equal transition time for all gate input signals across the net. A maximum allowable transition time would be determined and correlated with the interconnect Elmore Delay. Such methods are described in Julian Culetu, et. al, “A Practical Repeater Insertion Method, in High-speed VLSI Circuits”, proc. 35th DAC, 1998, and herein incorporated by reference.
The Elmore Delay is an efficient representation of the delay of an RC tree. A first order approximation of RC delay at any node i on an RC tree is given by the Elmore time constant
T
i
=
∑
k
-
1
n
R
ki
C
k
where Rki is the resistance of the portion of the path between the input and node i, that is common with the path between the input and node k, and Ck is the capacitance at node k.
The first order approximation of the waveform at node i is where Ti is the time constant Elmore Delay. The time at which the voltage at node i reaches any value Vx is determined by
V
i
=
V
DD
(
1
-
e
t
T
i
)
With the above theory in mind, prior art insertion methods utilized a repeater insertion algorithm in order to determine proper location for repeater cells. According to one such algorithm, once the distributed capacitance has been calculated, the Elmore Delay to each of the loads in the net is calculated. The repeater cells are inserted starting from the load with the highest Elmore Delay towards the driver, i.e. “bottom-up” search. While parsing through the RC net segment by segment, Elmore Delay is calculated considering a repeater cell as a driver of the segment. If the delay exceeds a maximum, a repeater cell is inserted into the segment forming a new subnet. The process starts again from the highest Elmore Delay load.
In the case of branching, the assumed branching node is moved from an assumed repeater cell input to a repeater cell output. This continues until the maximum delay is exceeded, in which case a repeater cell is inserted with its output at the branching node. The process continues until all segments in the net have been explored.
Another prior art algorithm technique for predicting repeater cell insertion location is described in John Lillis, et. al, “Timing Optimization for Multi-source Nets: Characterization and Optimal Repeater Insertion”, proc. 34th DAC, 1997, and herein incorporated by reference.
Prior art repeater insertion methods have been inadequate to achieve certain capacitance limitations between successive nodes. Significantly, they fail to produce satisfactory results in nets characterized by two or more fanout nets.
Furthermore, the prior art does not allow for “back-annotation” of the synthesis or layout software, thereby requiring additional input/output/biput pins to module definition. For example, each circuit module is characterized by a certain software module netlist. Generally, the ideal location for a repeater insert falls inside a module point. Insertion of a repeater cell at such point results in an additional input/output parameter for that module, which cannot be adequately represented in the netlist, i.e. the repeater cannot be “back-annotated” into the netlist software. As a result, the netlist for the module with the repeater cell must be regenerated.
Other repeater insertion methods were used for inter-hard macro block repeater insertion only. However, such methods cannot be used for Standard Cell circuits because new input/output pins are added to module definition after repeater insertion without module/region considering and thus do not allow for “back-annotation” of the synthesis or layout software.
Additional inadequacies in the prior art repeater insertion methods include lack of support for two or more sizes of repeater cells and are thereby restrained from handling various sized loads without significant time delay.
Finally, the prior art methods lack simple timing-driven-like repeater insertion techniques that reduce signal delay and eliminate the need for timing analysis.
In view of the above, it would be desirable to maintain minimal levels of interconnect delay and logic delay within a net.
Furthermore. it would be desirable to obtain proper repeater insertion that allows for the module to remain adequately represented by the netlist, without the need to regenerate the netlist, i.e. successful “back-annotation” into the software.
Finally, it would be desirable to allow for varying sizes of repeater cells to enable the handling of greater sized loads without significant interconnect delay and logic delay. Also, there is a need for simple timing-driven-like repeater techniques that reduce signal delay and eliminate the need for timing analysis.
SUMMARY OF THE INVENTION
Accordingly, one object of this invention is a method of inserting repeater cells, e.g. an inverter gate, into the two or more fanout nets, starting from one of the loads towards the driver, so that at any given point in the net, the interval of capacitance between any two nodes is no greater than a predetermined number of load units.
Another object of this invention is the ability to “back-annotate” to synthesis or layout software, repeater cell location, without the need for additional input/output pins to the module definition.
Yet another object of this invention is to allow for repeater insertion using two or more sizes of repeater calls.
A further object of this invention is to maintain short signal delay in the most critical fanout branches and eliminate the need for a timing analyzer while maintaining faster processing speed.
It is an advantage of this invention to maintain capacitance ratios between nodes for varying fanout circuit sizes.
It is another advantage of this invention to provide a more realistic analysis of net function in synthesis or layout software.
It is yet another advantage of this invention to reduce signal delay in nets with large loads.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated in carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.
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Chen et al. (“An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion”, Proceedings of European Design and Test Conference, 19
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Kik Phallaka
Smith Matthew
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