Method of placement for iterative implementation flows

Details Method of placement for iterative implementation flows Method of placement for iterative implementation flows

2007-04-18

2009-11-03

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07614025

ABSTRACT:
A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty sites of the target device within which the circuit design is to be implemented can be identified. The method also can include determining whether each of the plurality of empty sites of the target device has a routing conflict according to the routing information of the circuit design and generating a list specifying each empty site of the target device that has a routing conflict.

REFERENCES:
patent: 5825659 (1998-10-01), Nguyen et al.
patent: 7225116 (2007-05-01), Harn
patent: 7306977 (2007-12-01), Verma et al.
Xilinx, Inc.; “Development System Reference Guide”; Chapters 3, 4, 5; Copyright 1995-2005; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 55-140.

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