Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-06
2002-10-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06467072
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87119244, filed Nov. 20, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of placement and routing for an array device, and in particular to a method of placement and routing for an array device in which a schematic script file is created according to a circuit topology and a netlist corresponding to the array device, and then a routing program in coordination with the schematic script file is executed for automatic routing.
2. Description of the Related Art
Currently, great progress has been made in semiconductor technology. Any complicated circuit can be built in one single integrated circuit (IC) with an operating speed that is continuously increased. Due to an increase in IC complexity, feasibility testing methods for circuit designs is different from that for a conventional practical circuit connection. Current circuit designs are implemented with a computer-aided tool. For example, a circuit is designed by a circuit design program according to a specific specification, and then the designed circuit is tested for its own logic functions by a simulation program. After the logic functions of the designed circuit are determined to be exactly correct, a circuit placement and routing (P&R) is performed by a P&R tool so as to manufacture a real chip. Furthermore, it is necessary to take into consideration a time delay for a signal to transmit in the real circuit. Therefore, an RC value for each device must be extracted for implementing a time delay simulation, so that routing for the real circuit can meet the requirement of the time delay.
Even though the functions of current P&R tools are powerful, they do not perform well under some circumstances, such in an array device with a symmetrical structure. Generally, there are many kinds of array devices, such as a first in first out (FIFO) memory. An FIFO memory is used to store a queue of data or programs via the input terminals thereof. Then, the data or program can be read out in order via the output terminals of the FIFO memory. In order to ensure that the data can correctly flow between memory units in the FIFO memory, it is necessary to keep correct timing.
FIG. 1
is a block circuit diagram showing a structure of an FIFO memory
100
. As shown in
FIG. 1
, the FIFO memory
100
has a width of n-bit data B
0
-B
n-1
and a depth of m orders. Each memory unit
110
can store one-bit data while each column of memory units
110
consisting of an order of memory can store n-bit data. Each order of memory is controlled by a control unit
120
. In order to reduce the influence of a signal delay as much as possible, each control unit
120
is disposed in the center of each order of memory. The n-bit data B
0
-B
n-1
, are inputted to the first order of memory, and then are passed backward in order to the mth order of memory.
FIG. 2
is a block circuit diagram showing the memory unit
110
of FIG.
1
. Referring to
FIG. 2
, the memory unit
110
includes a buffer
112
and a latch circuit
114
. Obviously, data are input to the input terminal I of the memory unit
110
. The data coming from the buffer
112
is latched in the latch circuit
114
with the control of a control terminal E. Then, the latched data can be read out from an output terminal O thereof.
As an example, the FIFO memory
100
is an array device with a width of 64 bits and a depth of 32 orders; it has a total of 64×32 regularly arranged memory units. Each memory unit
110
of an order of memory is controlled by a control signal which is input to a control terminal E to latch data output from a previous order of memory. Therefore, to correctly transmit the data in order among the orders of memories, the control signal must be absolutely precise. Furthermore, as the correct operation of the FIFO memory
100
is substantially determined by the time delay of the control signal.
Since the properties of the array device cannot be processed particularly by an auto P&R tool, placement and routing for the array device is completely implemented by manual labor. Additionally, results obtained from manual P&R are much better than that from automatic P&R by a P&R tool.
FIG. 3
is a flow chart showing a method of placement and routing for an array device according to the prior art. Referring to
FIG. 3
, in step
310
, placement and routing for the array device is implemented by manual labor with a one-week working period per FIFO required.
In step
315
, the manual placement-and-routing completed array device is considered a black box in a P&R tool.
In step
320
, the P&R tool is executed to automatically complete placement and routing for an entire chip.
In step
325
, a data file obtained from executing the P&R tool is transferred into an intermediate file, such as a GDS format file, with a 2 to 3-day working period required. Moreover, the transferring process is interrupted each time a P&R error occurs. Only after correcting the error can the transferring process restart from the beginning. In other words, it takes much more time to complete step
325
.
In step
330
, an RC extraction is performed according to the middle file thereby creating a standard delay format (SDF) file for a subsequent circuit simulation verification.
Furthermore, it is inconvenient to perform manual placement and routing by using an auto P&R tool, such as an XO P&R software. Therefore, in the prior method of placement and routing for an array device, placement and routing for the array device is completed by manual labor in coordination with another software, such as an OPUS tool. After that, the manual placement-and-routing completed array device is considered a black box in the P&R tool, followed by the execution of the auto P&R tool for complete placement and routing of an entire chip. Since the manual placement-and-routing completed array device is considered a black box, RC extraction cannot be directly implemented. Therefore, a data file obtained from executing the routing program must be transferred into an intermediate file before RC extraction. In addition approximately a one-week working period is required for manual P&R, and a 2 to 3-day working period is necessary for file transferring. As a result, the cycle time of chip manufacturing is seriously affected.
In short, the prior method of placement and routing for an array device has the following disadvantages:
1. In order to cooperate with the properties of an array device, much more time must be taken for manual placement and routing, resulting in an influence on product development.
2. The manual placement-and-routing completed array device is considered a black box in a P&R tool. After automatically routing the entire chip by executing the routing program, the obtained data file must be transferred into an intermediate file for subsequent RC extraction. Since file transferring takes much more time, product development time is greatly increased.
SUMMARY OF THE INVENTION
In view of the above, an object of the invention is to provide a method of placement and routing for an array device. In the method, a schematic script file is created according to a circuit topology and a netlist which are corresponding to the array device, and then a P&R tool in coordination with the schematic script file is executed for an automatic routing. Thus, product development time can be greatly shortened.
To achieve the above-stated object, the method of placement and routing for an array device according to the invention includes the following steps. First, a netlist and an array structure specification for describing the array device is provided. A schematic script file is created for describing placement for the array device according to the netlist and the array structure specification. The schematic script file is loaded into a P&R tool. The P&R tool is executed to automatically route the array device.
Furthermore, the sc
Chang Yung-Chung
Wang Shu-Tzu
Yang Chun-Chih
J.C. Patents
Siek Vuthe
Thompson A. M.
Via Technologies Inc.
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