Method of performing timing-driven layout

Details Method of performing timing-driven layout Method of performing timing-driven layout

2005-05-31

2005-05-31

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06901567

ABSTRACT:
A timing-driven layout method is provided, which realizes timing error convergence toward zero without any timing constraint file. (a) An initial layout result is generated through placement of functional blocks of the circuit and routing of wiring lines therefor. (b) Wiring capacitance values of the respective blocks are calculated using the initial layout result. (c) Fan-out capacitance limitation values of the respective blocks are calculated using the wiring capacitance values of the blocks. Each of the fan-out capacitance limitation values represents a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value. (d) A driving capability of each of the blocks is compared with its fan-out capacitance limitation value, thereby generating a comparison result. (e) The blocks whose driving capabilities do not exceed their fan-out capacitance limitation values are defined as timing-error blocks based on the comparison result. (f) Circuit configuration of each of the timing-error blocks is changed based on its fan-out capacitance limitation value to decrease its propagation delay.

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