Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-28
2003-02-11
Smith, Matthew S. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06519752
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit devices and more particularly to an improved system and method for measuring parasitic resistances on multi-finger transistor devices.
2. Description of the Related Art
Conventional transistor devices include a source, drain and gate. When current flows across the gate, a connection is either made or broken between the source and drain. Therefore, the transistor acts as a switch to connect or disconnect electronic components. Multi-finger integrated circuit devices include a single gate that is connected to multiple source contacts and multiple drain contacts. The multi-finger transistor performs the same functions as a conventional transistor (e.g., acts as a switch). However, the multi-finger device takes up less space and has less resistance than the conventional transistor device of the appropriate width. For these reasons (and others) the use of multi-finger transistors is increasing.
The output parameters of device models are usually scaled with the device width. However, when the width of the fingers becomes too large, the error in the approximation produces unacceptable results. More specifically, as the fingers become wider, the delay of the signal traveling along the finger becomes large enough to affect the model's accuracy. Also any voltage drop caused by the device current flowing through the source resistor changes significantly the overdrive of the device and with this the current charging the load, hence requiring an accurate description of the source resistance. Most commercial extraction programs ignore the device resistance to avoid the large number of resulting devices. No conventional program has the ability to create one multi-finger device model with resistance included. Therefore, there is a need to maintain the models' accuracy (even for wide-fingered devices) without slowing the netlists simulation time.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a structure and method for performing parasitic extraction for a multi-fingered device comprising establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining which ones of the fingers and the sub-fingers have similar characteristics, combining the fingers and the sub-fingers that have the similar characteristics into combined fingers, and extracting the parasitic values from the fingers, the sub-fingers and the combined fingers into the final netlist.
The similar characteristics are comprised of electrical resistivity of the fingers and the sub-fingers. Each of the sub-fingers has a width no greater than the maximum processing width. Fingers exceeding the maximum width would produce erroneous results in the extraction process. From the relative geometric position of the sub-fingers to each other, the extraction program decides which ones have similar resistivities and then assigns names reflecting this situation to each of the sub-fingers. These names are then picked up during the recombination process. In this way only sub-fingers with similar characteristics are combined. The time required for the simulation of the extracted netlist is significantly reduced by the combining process.
REFERENCES:
patent: 5754826 (1998-05-01), Gamal et al.
patent: 6209123 (2001-03-01), Maziasz et al.
Bakker William C.
Dewey, III L. William
Habitz Peter A.
McCullen Judith H.
Seibert Edward W.
Do Thuan
International Business Machines - Corporation
Kotulak, Esq. Richard M.
McGinn & Gibb PLLC
Smith Matthew S.
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