Method of performing mask-writer tuning and optimization

Details Method of performing mask-writer tuning and optimization Method of performing mask-writer tuning and optimization

2009-04-02

2011-11-08

Lin, Sun (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Layout generation

C716S050000, C716S051000, C716S054000

Reexamination Certificate

active

08056028

ABSTRACT:
A model-based tuning method for tuning a first mask writer unit utilizing a reference mask writer unit, each of which has tunable parameters for controlling mask writing performance. The method includes the steps of defining a test pattern and a mask writing model; generating the test pattern utilizing the reference mask writer unit and measuring the mask writing results; generating the test pattern utilizing the first mask writer unit and measuring the mask writing results; calibrating the mask writing model utilizing the mask writing results corresponding to the reference mask writer unit, where the calibrated mask writing model has a first set of parameter values; tuning the calibrated mask writing model utilizing the mask writing results corresponding to the first mask writer unit, where the tuned calibrated model has a second set of parameter values; and adjusting the parameters of the first mask writer unit based on a difference between the first set of parameter values and the second set of parameter values.

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Japanese Office Action mailed May 18, 2011 in corresponding Japanese Patent Application No. 2009-092538.

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