Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-05-05
2002-02-05
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S735000, C714S824000
Reexamination Certificate
active
06345371
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to communication systems, and more particularly, to a method and apparatus for performing diagnostic procedures on queue structures used for storing received data in communication systems.
2. Description of the Related Art
Modern communication systems, such as computer networking systems or communication networks, provide constant transmission of data between end stations and/or intermediate stations such as routers and signal amplifiers. Computer networking systems, such as packet switched networks (e.g., Ethernet networks), often require transmission of data to a single end station or to multiple end stations within the network. The data originates from a user program, and is segmented into multiple data frames and subsequently transmitted in order to simplify processing and minimize the retransmission time required for error recovery. For example, in a conventional e-mail system, a user may desire to send the same e-mail message to four different users that are connected to the e-mail system. Accordingly, the identical data would be directed to multiple end stations.
Packet switched computer networks typically employ a network switch that receives and forwards frame data to individual and/or multiple end stations. The switch makes forwarding decisions upon receipt of frame data based on information contained in a header of the frame data. For example, if a received frame data is to be transmitted to a number of end stations, the switch must make the forwarding decision to forward the frame data to the ports of the correct end stations. Depending on the specific implementation and/or characteristic of the networking system (i.e., data transfer rate, traffic intensity), buffers must be provided for temporary storage of the frame data, received by the switch, until forwarding decisions can be made. The buffers used to store the frame data are often implemented as first in, first out (FIFO) queues.
One concern in systems that implement FIFO queues to store data (frame data or other types of data) is assurance of the integrity of the data from the time they are received and stored in the queue, until they are transmitted out of the queue. This concern is particularly difficult to satisfy if the switch has a number of ports through which information can be transmitted, or operates at a high transfer rate (e.g., 100 Mb/sec or higher). For example, if the frame data is lost or damaged, the end stations will receive inaccurate information, hence requiring retransmission of the lost frame data and increasing traffic intensity.
A design consideration for such systems is to provide a mechanism wherein the structure and reliability of the queue may be periodically tested to ensure integrity of frame data during normal operations. One method of testing the integrity of the queue structure and its function is to provide random access to the data stored therein and verify that the stored data conforms to the original data input to the queue structure. For example, ten entries may be input to the queue structure and randomly accessed for verification purposes.
One difficulty associated with such an approach is the complexity of the logic that must be constructed to implement random access to different entries in the queue structure. Another difficulty associated with such an approach stems from the fact that the queue structure is implemented in a FIFO manner. Consequently, randomly accessing different locations of the queue structure in real time can often result in disruption of the logic used to maintain and access the queue structure. Additionally, once such a disruption occurs, data stored in the queue structure can become disordered, hence eliminating its FIFO nature. In other situations, the data stored in the queue structure may become completely inaccessible, and the switch must be reset.
Accordingly, a primary disadvantage associated with current methods of transmitting data in communication systems, such as a packet switched computer networking system, is the inability to perform diagnostic procedures on buffers used to store data, such as FIFO queue structures, and efficiently determine whether the integrity of received data is maintained within the queue structure.
DISCLOSURE OF THE INVENTION
There is a need for an arrangement for accessing entries in a queue structure of a communication system and detecting whether the data contained in the accessed entry is identical to the data input to the queue structure.
These and other needs are addressed by the present invention, wherein data input to a queue structure is tested in a FIFO manner to ensure the functionality of the queue structure and integrity of the data.
In accordance with one aspect of the invention, a method for testing the functionality of a queue structure comprises the steps: inputting data into an input portion of the queue structure; transferring the data into an output portion of the queue structure; retrieving the data from the output portion of the queue structure; and comparing the retrieved data with the input data to determine the functionality of the queue structure by verifying that the input data has not been altered during the step of transferring. The present arrangement thus determines the functionality of the queue structure by verifying that data input to the queue structure is not corrupted or modified prior to retrieval from the output portion of the queue structure. Because the functionality of the queue structure is determined by accessing the data present at the output portion, the need to randomly access entries within the queue structure and the logic circuitry associated therewith is eliminated.
According to one specific implementation of the present invention, the queue structure may be tested in real time by inputting the retrieved data back into the queue. This allows a designer to test the functionality of the queue structure without the need to shut down or suspend operation of the system. According to another implementation of the present invention, the circuitry normally used to retrieve data may be disabled, while a diagnostic register is enabled to retrieve data from the queue structure. This provides the designer with the flexibility to test a prescribed number of entries and terminate the test whenever desired.
In accordance with another aspect of the present invention, an apparatus for testing the functionality of a queue structure comprises: an input circuit for inputting data into an input portion of the queue structure; a data transfer circuit for transferring data from the input portion to an output portion of the queue structure; an output circuit for retrieving data from the output portion of the queue structure; and a comparison logic circuit for comparing the retrieved data with the input data to determine the integrity thereof by verifying that the input data has not been altered by the data transfer circuit. The present apparatus provides a simplified arrangement for testing the functionality of the queue structure by accessing the data present at the output portion of the queue structure, hence eliminating the need to randomly access entries within the queue structure and the logic circuitry necessary to implement such random access.
Additional advantages and novel features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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S. Barbagallo, M. L. Bodoni, D. Medina, G. De Blasio, M. Ferloni, F.
Advanced Micro Devices , Inc.
De'cady Albert
Torres Joseph
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