Method of performing bus arbitration between control chips...

Details Method of performing bus arbitration between control chips... Method of performing bus arbitration between control chips...

2000-11-13

2004-01-20

Rinehart, Mark H. (Department: 2181)

Electrical computers and digital data processing systems: input/

Access arbitrating

C710S241000, C710S242000, C710S243000, C710S244000

Reexamination Certificate

active

06681279

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88119832, filed Nov. 15, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer technology, and more particularly, to a method of performing bus arbitration between two control chips in a chipset with preemptive capability.
2. Description of Related Art
FIG. 1
is a schematic diagram showing the architecture of a computer system with a PCI bus system. As shown, the computer system includes a CPU
10
and a primary memory unit
11
, and is coupled via a host bridge
12
to a PCI bus system
14
which is further coupled to a number of PCI-compliant units, such as a graphics adapter
16
a
, an expansion-bus bridge
16
b
, a LAN adapter
16
c
, and a SCSI host bus adapter
16
d
. Each of these adapters can issue a request (REQ) to use the PCI bus system
14
when transaction over the PCI bus system
14
is intended. The request signal is first sent to the host bridge
12
for arbitration. When the request is granted, the host bridge
12
will return a grant signal (GNT) to grant the use of the PCI bus system
14
by the request-issuing adapter.
The data communication between the host bridge
12
and the PCI-compliant units
16
a
,
16
b
,
16
c
,
16
d
over the PCI bus system
14
is achieved through the use of a set of control signals, including FRAME (cycle frame), AD (address), CBE (command/byte enable), REQ (request), GNT (grant), IRDY (initiator ready), TRDY (target ready), and DEVSEL (device select). One example of the timings and waveforms of these signals is illustrated in FIG.
2
. In this specification, the term “initiator” refers to the unit that initiates a request to use the PCI bus system
14
, which can be either the host bridge
12
or any one of the PCI-compliant units
16
a
,
16
b
,
16
c
,
16
d
, while the term “target” refers to the unit that the initiator intends to transfer data thereto.
The FRAME signal is issued by the initiator to indicate the starting time and the duration of the intended data communication over the PCI bus system
14
. When the FRAME signal is set to LOW state, it enables the initiator to gain access to the PCI bus system
14
. During the address phase, the initiator will issue the AD signal indicative of the valid address and the CEE signal (CBE[
3
:
0
] for enabling the command/byte transfer. The CBE signal is composed of 4 bits which can represent 16 different commands. The CBE signal format is rally described in the PCI standard, so description thereof will not be further detailed. Subsequently, during the data phase, the initiator will send out the AD signal representative of the data to be transferred over the PCI bus system
14
to the target. When the FRAME signal is disabled, it indicates that the transaction is completed. When the initiator is ready to send out data, the IRDY signal is enabled; and when the target is ready to receive the data, the TRDY signal is enabled. During read operations, the enabling of the IRDY signal indicates that the initiator is ready to receive data from the target; whereas during write operations, the enabling of the TRDY signal indicates that the target is ready to receive data. When the target wants to stop the transaction, it issues the STOP signal to the initiator.
FIG. 2
shows an example of the waveforms and timings of the above-mentioned signals specified by the PCI standard for an initiator to perform a read operation on a target. In this signal diagram, the duration indicated by the reference numeral
20
is called a bus transaction period, during which the data exchange is carried out. The bus transaction period
20
includes an address phase
22
and a number of data phases
24
a
,
24
b
,
24
c
. The data phases
24
a
,
24
b
,
24
c
each include a wait cycle, respectively designated by the reference numerals
26
a
,
26
b
,
26
c
, and a data transfer cycle, respectively designated by the reference numerals
28
a
,
28
b
,
28
c.
The PCI bus system is clocked by a system clock signal CLK. During the first period T
1
of CLK, the initiator issues a FRAME signal to indicate that it intends to transfer data to a certain target. Subsequently, the initiator sends out the AD signal indicative of the start address specifying the target where the initiator intends to read data. After this, the initiator sends out the CBE signal. The CBE signal is in the enabled state during all the data phases
24
a
,
24
b
,
24
c
. During the next period T
2
, the initiator issues the IRDY signal indicating that it is ready for data communication. However, since this period is the wait cycle
26
a
in the data phase
24
a
, the target is still not ready. During the next period T
3
, the target is ready and hence issues the TRDY signal indicative of this condition. This causes the target to transfer data to the initiator during the data transfer cycle
28
a
. During the next period T
4
, the target disables the TRDY signal, indicating that the transfer of the current piece of data is completed, and then prepares the next piece of data for transfer. This is the wait cycle
26
b
of the data phase
24
b
. During the next period T
5
, the target enables the TRDY signal again, indicating that it is ready to transfer data. When the IRDY signal is also enabled during the data transfer cycle
28
b
, the initiator starts to read data from the target. During the next period T
6
, the initiator disables the IRDY signal to indicate that it is unable to receive any more data. However, since the TRDY signal is still in the enabled state, the wait cycle
26
c
is activated by the initiator. During the next period T
7
, the initiator is again ready to receive data and hence enables the IRDY signal. When the TRDY signal is also enabled during the data transfer cycle
28
c
, the initiator starts to read data from the target. This completes the read operation.
One drawback to the data communication specified by the PCI standard, however, is that it requires the use of complex control signals with difficult-to-handle waiting states and arbitration. Moreover, it requires at least 45 to 50 pins on the control chipset to handle all the signals specified by the PCI standard. In the system of
FIG. 1
, for example, the host bridge
12
is implemented by a North Bridge chip, while the expansion-bus bridge
16
b
is implemented by a South Bridge chip. In most PCs, the South Bridge chip is an indispensable control chip.
In many cases, the transaction between the various chips in a chipset, for example between a South Bridge chip and a North Bridge chip, may use just a small part of the full set of functions specified by the utilized bus standard. The great number of functions are provided in hope that the bus architecture can be adapted for use in many various kinds of environments. This provision, however, may prevent some advanced functions from being incorporated into the bus architecture. As IC packaging technology advances, a control chipset may incorporate an increased number of chips in a single device, but this would also undesirably increase the number of external connecting pins. There exists therefore a need for a bus architecture that can help speed up the transactions between the various chips in a chipset while reducing the total number of external connecting pins of the chipset to minimum. For example, there exists a need for a reduced set of signal lines in the bus between a South Bridge chip and a North Bridge chip, but which is still PCI-compatible so that it can be used together with existing components.
Whenever a chip wants to transfer data, it will issue a request to use the bus. It can then use the bus for data transfer only after it gains the control of the bus. In the event that a chip has high volume video/audio data to transfer over the bus but cannot gain control of the bus in a short time due to the bus being lengthily used by another chip, it would undoubtedly degrade the overall system communication performance.
SUMMARY OF THE INVENTI

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