Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-02-22
2001-12-11
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S161000, C438S484000, C438S586000
Reexamination Certificate
active
06329227
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of patterning an organic polymer film and a method for fabricating a semi-conductor device by utilizing the patterning method.
Recently, millimeter wave bands, or ultrahigh frequency bands of 30 GHZ or more, are frequency resources that should hopefully be developed for a broad variety of applications including multi-media mobile telecommunications units and radio frequency LANs. To ensure a sufficient gain for an FET in ultrahigh frequency bands like these, the gate electrode of the FET should have its length and resistance both reduced. On top of that, a parasitic capacitance associated with the gate electrode should also be reduced. A T-shaped (or mushroom-shaped) gate electrode would be a best choice so far among various measures for reducing the gate length and gate resistance. So a T-gate electrode is adopted more and more often for that purpose.
A typical known semiconductor device including a T-gate electrode will now be described with reference to
FIG. 3
, which schematically illustrates a cross-sectional structure for a known semiconductor device of this type.
As shown in
FIG. 3
, the device includes semi-insulating GaAs substrate
51
, epitaxial layer
52
deposited on the substrate
51
and a T-gate electrode
56
formed on the epitaxial layer
52
. The bottom of the T-gate electrode
56
makes a Schottky contact with the surface of the epitaxial layer
52
. A pair of ohmic electrodes
55
is further formed on, and makes an ohmic contact with, the epitaxial layer
52
. For the other parts that are not covered with the T-gate electrode
56
or ohmic electrodes
55
, the upper surface of the epitaxial layer
52
is covered with an interlevel dielectric film
54
of SiO
2
. Also, to electrically isolate the illustrated device from adjacent ones, the epitaxial layer
52
is surrounded with an isolation region
53
.
A method for fabricating the known semiconductor device will be described next with reference to
FIGS. 4A through 4G
, which illustrate respective process steps for fabricating the device shown in FIG.
3
.
First, as shown in
FIG. 4A
, an epitaxial layer
52
is deposited on a semi-insulating GaAs substrate
51
by an MOCVD or MBE process, and an isolation region
53
is defined by implanting dopant ions into a selected region of the substrate.
Next, as shown in
FIG. 4B
, an insulating film
54
of SiO
2
is deposited on the epitaxial layer
52
by a CVD process, and then a photoresist
55
, having an opening
55
a
with a width of 0.1 &mgr;m, is defined on the insulating film
54
.
Thereafter, as shown in
FIG. 4C
, an opening
54
a
is formed in the insulating film
54
by dry-etching the film
54
anisotropically using the photoresist
55
as a mask, and then the photoresist
55
is removed as shown in FIG.
4
D.
Subsequently, as shown in
FIG. 4E
, parts of the insulating film
54
, where ohmic electrodes will be formed, are removed to form another pair of openings, and then ohmic electrodes
56
are formed on the particular areas of the epitaxial layer
52
that are exposed inside the openings. Next, another photoresist
57
with an opening
57
a
is defined as shown in FIG.
4
F.
Finally, a metal film (not shown) is deposited over the photoresist
57
so that the opening
57
a
is filled with the metal, and then the photoresist
57
is removed along with the excessive metal, thereby forming a T-gate electrode
58
as shown in FIG.
4
G.
This device includes the T-gate electrode
58
, and can have a shorter gate length and reduced gate resistance. However, the insulating film
54
is made of SiO
2
with a dielectric constant of about 4.0, so the gate parasitic capacitance is not so small. That is to say, this device has a large fringe capacitance due to the particular shape of the gate electrode
58
and the material of the insulating film
54
.
To reduce the fringe capacitance of the gate electrode
58
, the insulating film
54
should preferably be made of a material with a lower dielectric constant (which will be herein called a “low-&kgr; material”). An organic polymer may be used as an alternative material for the insulating film
54
, because an organic polymer has a dielectric constant lower than that of SiO
2
. However, if the above process is performed as it is just by substituting an organic polymer for SiO
2
, then it is difficult to form the opening
54
a
at a desired small size.
In the above process, the opening
54
a
is formed in the insulating film
54
by dry-etching the film
54
anisotropically using the photoresist
55
with the opening
55
a
as a mask as shown in FIG.
4
C. Then, the opening
54
a
of the insulating film
54
will usually be greater in width than the counterpart
55
a
of the photoresist
55
. This is also true even when the insulating film
54
is made of an organic polymer. In that case, the width of the resultant opening
54
a
will be no less than about 0.7 &mgr;m, for example. That is to say, the opening
54
a
cannot have a width as small as 0.3 &mgr;m or less (e.g., 0.1 &mgr;m) according to the known process.
To avoid this problem, the opening
54
a
may be formed by a lift-off technique, not by using the photoresist
55
having the opening
55
a.
But we found that another problem is caused by doing so.
FIGS. 5A and 5B
are cross-sectional views illustrating the process steps of forming an opening by a lift-off technique. First, a substrate
61
is prepared, and a fine-line resist pattern
62
is defined on the substrate
61
by a photolithographic technique as shown in FIG.
5
A. Next, as shown in
FIG. 5B
, an organic polymer film
63
is deposited over the substrate
61
. However, since an organic polymer is usually liquid, the resist pattern
62
cannot be lifted off as it is. That is to say, even if the resist pattern
62
is lifted off, the film
63
of the liquid organic polymer will planarize itself after that. As a result, no opening can be formed in the organic polymer film
63
. To form an opening in the organic polymer film
63
by a lift-off technique, the liquid organic polymer should be cured by annealing it at 200° C. or more. However, the resist pattern
62
is usually cured or deformed at about 150° C. Accordingly, it is meaningless to cure the liquid organic polymer by annealing it at 200° C. or more.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of patterning an organic polymer film in such a manner that the film can have an opening of a very small width.
It is another object of the invention to provide a method for fabricating a semiconductor device so that the gate electrode will have a reduced fringe capacitance.
An inventive organic polymer film patterning method includes the steps of: defining a resist film on a selected area of a substrate; depositing an organic polymer film over the substrate by a plasma CVD process so that the resist film is covered with part of the organic polymer film; and removing the resist film along with the part of the organic polymer film that has covered the resist film.
In one embodiment of the present invention, the organic polymer film is preferably a low-&kgr; film with a dielectric constant lower than that of SiO
2
.
In this particular embodiment, the low-&kgr; film may be made of a cyclobutane derivative.
More specifically, the cyclobutane derivative is preferably benzocyclobutene (BCB).
In an alternative embodiment, the low-&kgr; film may also be made of a fluoropolymer.
In still another embodiment, the organic polymer film is preferably deposited within an inert gas ambient.
In yet another embodiment, a deposition temperature of the organic polymer film is preferably lower than a temperature at which the resist film starts to degrade.
An inventive method for fabricating a semiconductor device includes the steps of: defining a resist film on a selected area of a substrate; depositing an organic polymer film over the substrate by a plasma CVD process so that the resist film is covered with part of the organic polymer film;
Anda Yoshiharu
Kawashima Katsuhiko
Nishitsuji Mitsuru
Tanaka Tsuyoshi
Lebentritt Michael
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Robinson Eric J.
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