Method of patterning lines in semiconductor devices

Details Method of patterning lines in semiconductor devices Method of patterning lines in semiconductor devices

2001-12-04

2002-12-03

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S673000

Reexamination Certificate

active

06489237

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for creating very fine lines as part of the process of creating semiconductor devices.
(2) Description of the Prior Art
The continued effort to reduce device dimensions and to therewith improve device electrical performance requires high accuracy formation of conductive lines, conductive patterns and conductive connectors of sub-micron dimensions. These sub-micron conductive elements may be elements of an individual semiconductor device or may be elements that form conductive interconnects between co-functional semiconductor devices within one larger package.
A conventional process for creating sub-micron conductive lines and patterns uses a lift-off process. This process is briefly highlighted using
FIGS. 1 and 2
.
Shown in the cross section of
FIG. 1
are the following elements:
10
, the surface of a substrate, typically a monocrystalline silicon substrate
12
, a layer of insulation that is created over the surface of substrate
10
14
, a layer of conductive material in which the sub-micron conductive lines and patterns are to be created; the conductive material
14
can comprise metal, polysilicon, amorphous silicon or any other semiconductor compatible conductive layer
16
, a layer of exposure sensitive material that is used for the creation of an etch mask over the surface of layer
14
; layer
16
typically comprises photoresist, which can be developed by exposing the irradiated surface of layer
16
to a solvent that is capable of dissolving the irradiated portion (that is a positive-tone photoresist has been used) or that that is capable of dissolving the non-irradiated portion (that is a negative-tone photoresist has been used).
The preferred technology that is applied for the creation of the openings
15
in layer
16
of exposure sensitive material is photolithography. Key parameters in this exposure's the cross section of openings
15
, that is the feature width of the created sub-micron conductive lines and patterns, and the distance between openings
15
, which is the separation of the created sub-micron conductive lines and patterns. Significant improvements in the art of photolithography have enabled continued reduction of the critical dimensions of the sub-micron conductive lines and patterns. Efforts continue to be dedicated to improvements of photolithographic technology. These efforts have led to for instance the use of and improvements of phase shifting masks and alternate phase shifting masks, which reduce proximity effects of the light beams that are used for the exposure of an exposure sensitive surface such as the surface of layer
16
,
FIG. 1
, of photoresist. These efforts however result in significant increases in the cost of creating semiconductor devices, which is a trend that must be avoided in the highly cost-sensitive and competitive semiconductor manufacturing industry.
Another approach that has been used to create sub-micron conductive lines and patterns is to increase the frequency of the source of energy that is used with photolithography processes. As such have been applied the use of I-line (365 nm) exposure, combined with high-resolution photoresist and the use of Deep UV (248 nm) exposure. Both of these methods however result in an increased manufacturing cost.
The sub-micron conductive lines and patterns of
FIG. 1
are created by etching (lifting-off) the underlying conductive layer
14
,
FIG. 1
, in accordance with the pattern that has been created in the exposure sensitive layer
16
, after which the mask
16
can be removed from the surface of the created pattern
14
, FIG.
2
.
The invention provides a method that addresses the above stated concerns relating to the creation of sub-micron conductive lines and patterns by using photolithography technology. The method of the invention alleviates requirements that are typically imposed on the equipment that is used during the process of photolithographic exposure for the creation of sub-micron conductive lines and patterns.
U.S. Pat. No. 6,100,014 (Lin et al.) shows a photo process to form a small opening using spacer on a resist layer.
U.S. Pat. No. 6,239,008 (Yu) shows a photo process to form a dense pattern by a double deposition process.
U.S. Pat. No. 4,702,792 (Chow et al.), U.S. Pat. No. 5,888,904 (Wu), U.S. Pat. No. 4,496,419 (Nulman et al.), U.S. Pat. No. 4,954,218 (Okumura et al.), U.S. Pat. No. 4,759,822 (Vetanen et al.) are related processes.
SUMMARY OF THE INVENTION
A principle objective of the invention is to create sub-micron conductive lines and patterns using a cost-competitive method.
Another objective of the invention is to alleviate requirements that are typically imposed on photolithographic equipment that is used for the creation of sub-micron conductive lines and patterns.
In accordance with the objectives of the invention a new process is provided for the creation of sub-micron conductive lines and patterns. A conductive layer is deposited over the surface of a substrate, a sacrificial layer that differs with the conductive layer in etch characteristics is deposited over the surface of the conductive layer. The sacrificial layer is patterned and etched, creating an opening in the sacrificial layer that aligns with but is larger in cross section than the to be created sub-micron conductive lines and patterns. A spacer layer is deposited over the surface of which a hard mask layer is deposited, filling the opening in the sacrificial layer. The hard mask layer is polished down to the surface of the spacer layer, leaving the hard mask layer in place overlying the spacer layer inside the opening created in the sacrificial layer. Using the hard mask layer as a mask, the spacer layer, the sacrificial layer and the conductive layer are etched, leaving in place the hard mask layer overlying the etched spacer layer, which overlies the etched conductive layer. The etched conductive layer now has a cross section that equals the cross section of the hard mask layer. Removing the hard mask layer and the spacer layer leaves the conductive layer in place, having a cross section that is significantly smaller than the cross section of a conventionally created sub-micron conductive lines and patterns.


REFERENCES:
patent: 4496419 (1985-01-01), Nulman et al.
patent: 4702792 (1987-10-01), Chow et al.
patent: 4759822 (1988-07-01), Vetanen et al.
patent: 4954218 (1990-09-01), Okumura et al.
patent: 5371410 (1994-12-01), Chen et al.
patent: 5888904 (1999-03-01), Wu
patent: 6100014 (2000-08-01), Lin et al.
patent: 6103623 (2000-08-01), Lien et al.
patent: 6239008 (2001-05-01), Yu et al.
patent: 6268287 (2001-07-01), Young et al.

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