Method of patterning a submicron semiconductor layer

Details Method of patterning a submicron semiconductor layer Method of patterning a submicron semiconductor layer

1997-10-20

2000-08-01

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438626, 438631, 438634, 438637, H01L 214763

Patent

active

060966343

ABSTRACT:
A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. An interlevel dielectric layer is formed over the surface of the integrated circuit. A planarizing layer is formed over the interlevel dielectric layer. A photoresist layer is formed and patterned over the planarizing layer. The planarizing layer is etched to form openings exposing selected portions of the interlevel dielectric layer, wherein each opening has the same lateral dimensions. The photoresist and planarizing layers are then removed. The interlevel dielectric layer is etched in the openings to expose portions of the underlying integrated circuit.

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