Method of partitioning an integrated circuit design for...

Details Method of partitioning an integrated circuit design for... Method of partitioning an integrated circuit design for...

2006-09-12

2006-09-12

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07107559

ABSTRACT:
A method of partitioning an integrated circuit design for physical design verification includes steps of receiving as input a representation of an integrated circuit design having a number of physical design layers and a composite run deck specifying rule checks to be performed on the integrated circuit design. The composite run deck is partitioned into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum. The representation of the integrated circuit design is parsed to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks. The filtered data deck is generated as output for each of the partitioned run decks.

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