Method of partial reconfiguration of a PLD in which only...

Details Method of partial reconfiguration of a PLD in which only... Method of partial reconfiguration of a PLD in which only...

2001-04-24

2004-12-28

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Reconfiguration

C716S030000, C714S016000

Reexamination Certificate

active

06836842

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to configuration of programmable logic devices (PLDs), and more particularly to partial run-time reconfiguration of PLDs.
BACKGROUND
Usage of programmable logic devices (PLDs), in particular, field programmable gate arrays (FPGAs), is expanding from implementation of static circuit designs to in-system, run-time reconfiguration (RTR) applications. The field of reconfigurable computing has advanced steadily for the past decade, using FPGAs as the basis for high-performance reconfigurable systems. Run-Time Reconfigurable (RTR) systems distinguish themselves by performing circuit logic and routing customization at run-time. RTR systems using FPGAs are expected to result in systems that require less hardware, less software, and fewer input/output resources than traditional FPGA-based systems.
For runtime reconfigurable applications to proliferate, designers must have access to tools that support the development of such applications. JBits software from Xilinx, for example, provides an environment for designing and deploying applications that support runtime reconfiguration. JBits provides a Java-based application programming interface (API) for generating configuration data, loading the configuration data into an FPGA, and reading back configuration and state data from the FPGA. Thus, portable run-time reconfiguration applications can be developed using object-oriented techniques.
With RTR systems, the time required to generate the programming bitstream may be critical from the viewpoint of a user who is waiting for the FPGA to be reconfigured, as compared to traditional configuration of FPGAs where the time taken to generate a programming bitstream is generally not real-time critical. Thus, it may be acceptable in traditional implementation scenarios to take hours to generate a programming bitstream using traditional configuration methods. In an RTR environment, however, it is expected that the reconfiguration process require no more than a few seconds or even a fraction of a second.
Some FPGAs, for example, Virtex® FPGAs from Xilinx, are partially reconfigurable, which assists in reducing the time required for reconfiguration. For some design changes only a small portion of the configurable resources change. Thus, reconfiguring the entire device to implement such changes would be unnecessarily time consuming. With partial reconfigurability, the capability is provided to configure only those portions needing configuration.
Partial reconfigurability is especially important in a run-time reconfiguration application since reconfiguration is performed at runtime. Accessible and efficient support of partial reconfiguration capabilities at the application program level are essential for the development of new run-time reconfiguration applications.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
In various embodiments, the invention supports partial run-time reconfiguration applications for programmable logic devices (PLDs). The methods of an API that supports run-time reconfiguration applications manage configuration data for partial reconfiguration, and the API saves in application memory a copy of the configuration data used to configure the PLD. As the application updates selected portions of the in-memory configuration data, the API tracks which portions of the configuration data changed. When the application initiates reconfiguration of the PLD, the API partially reconfigures the PLD with the tracked changed portions of the configuration data. For readback of configuration data from the PLD, the API tracks which portions of in-memory configuration data are synchronized with the PLD.
It will be appreciated that various other embodiments are set forth in the Detailed Description and claims which follow.


REFERENCES:
patent: 5524205 (1996-06-01), Lomet et al.
patent: 5946219 (1999-08-01), Mason et al.

Affiliated with

Also associated with

Rating

Method of partial reconfiguration of a PLD in which only... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of partial reconfiguration of a PLD in which only..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of partial reconfiguration of a PLD in which only... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3299295