Method of packaging integrated circuits

Details Method of packaging integrated circuits Method of packaging integrated circuits

2007-12-21

2009-11-03

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

Small lead frame for connecting a large lead frame to a...

C257S666000, C257S673000, C257SE23031, C257SE23042, C257SE23043

Reexamination Certificate

active

07612435

ABSTRACT:
A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead.

REFERENCES:
patent: 5530282 (1996-06-01), Tsuji
patent: 6781243 (2004-08-01), Li et al.
patent: 2007/0132075 (2007-06-01), Masumoto

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