Method of packaging integrated circuit chips, and integrated cir

Details Method of packaging integrated circuit chips, and integrated cir Method of packaging integrated circuit chips, and integrated cir

1985-05-20

1986-12-09

Pellinen, A. D.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

29832, 357 81, 361414, H05K 111

Patent

active

046284060

ABSTRACT:
An integrated circuit package comprises at least two integrated circuit chips each having a plurality of contact pads arranged in a first pattern on the interconnect face of the chip, and an elastic sheet-form interconnect member. The interconnect member has at least two main face areas, associated with the chips respectively, and comprises dielectric material and conductor runs supported by the dielectric material in mutually electrically insulated relationship and having termination points arranged in at least two second patterns at the main face areas respectively and corresponding with the first patterns respectively. The interconnect face of each is in confronting relationship with the associated main face area of the interconnect member, and the contact pads of the chip and the termination points of the associated main face area are in mutually registering relationship. A metallurgical bond is formed between each contact pad and the corresponding termination point. The assembly of the interconnect member and the integrated circuit chips is placed between, and in pressure contact with, first and second essentially rigid enclosure members, with the first enclosure member in thermally-conductive contact with the back face of at least one of the chips and being made of a material that has good thermal conductivity.

REFERENCES:
Dougherty, "Control of Thermal Coefficient of Expansion of Substrate Materials", IBM Tech. Disclosure Bulletin, vol. 19, No. 8, 1/77 p. 3048.
Johnson et al., "Multilayer Ceramic Fixed Layer Substrate Design", IBM Tech. Disclosure Bulletin, vol. 22, No. 5, 10/79, pp. 1841-1842.

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