Method of packaging and interconnection of integrated circuits

Details Method of packaging and interconnection of integrated circuits Method of packaging and interconnection of integrated circuits

2005-08-18

2009-11-17

Parekh, Nitin (Department: 2811)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S613000, C438S615000, C438S666000, C257S737000, C257SE23028

Reexamination Certificate

active

07618844

ABSTRACT:
A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

REFERENCES:
patent: 5053195 (1991-10-01), MacKay
patent: 5225157 (1993-07-01), McKay
patent: 5406025 (1995-04-01), Carlstedt
patent: 5468681 (1995-11-01), Pasch
patent: 5672913 (1997-09-01), Baldwin et al.
patent: 6008542 (1999-12-01), Takamori
patent: 6259036 (2001-07-01), Farnworth
patent: 6323058 (2001-11-01), Murakamz et al.
patent: 6495441 (2002-12-01), Kitajima et al.
patent: 6554923 (2003-04-01), Bhattacharya et al.
patent: 6609652 (2003-08-01), MacKay et al.
patent: 7161237 (2007-01-01), Lee
patent: 2002/0050652 (2002-05-01), Akram et al.
patent: 2002/0142575 (2002-10-01), Lee
patent: 2002/0192936 (2002-12-01), Ball
patent: 2003/0032217 (2003-02-01), Farnworth et al.
patent: 2003/0134450 (2003-07-01), Lee
patent: 2005/0150936 (2005-07-01), Mackay
patent: 2005/0215045 (2005-09-01), Rinne et al.

Affiliated with

Also associated with

Rating

Method of packaging and interconnection of integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of packaging and interconnection of integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of packaging and interconnection of integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4055034