Method of packaging a high voltage device array in a multi-chip

Details Method of packaging a high voltage device array in a multi-chip Method of packaging a high voltage device array in a multi-chip

1995-11-24

1998-04-14

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

257701, 257725, 257783, 361813, 361820, H01L 23495, H01L 2334

Patent

active

057395829

ABSTRACT:
A method in which several high voltage chips may be packaged within a single, typically low voltage plastic package. The high voltage chips are packaged to remain electrically isolated from each other to avoid undesirable side effects such as arcing between the chips but able to share electronic data and communicate with each other electronically through their input and ouput nodes. Due to the unique packaging method, the typically low voltage plastic packaging can be made to withstand operating voltages up to 35 times greater than previously attained by such low voltage plastic packaging.

REFERENCES:
patent: 4466181 (1984-08-01), Takishima
patent: 4989063 (1991-01-01), Kolesar, Jr.
patent: 5559363 (1996-09-01), Immorlica, Jr.
patent: 5572065 (1996-11-01), Burns
patent: 5625235 (1997-04-01), Takiar

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