Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-12
2003-11-18
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06651224
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a technology utilized when designing a circuit which includes a signal supplying source (e.g., clock signal supplying source) within the circuit and a plurality of elements (e.g., flip-flop cells) supplied with a signal from the signal supplying source.
In more particularly, the present invention relates to a method of optimizing signal lines within the circuit, an optimizing apparatus and a recording medium having stored therein an optimizing program which are utilized when automatically synthesizing signal lines (net) connecting the signal supplying source to each of the elements in which a buffering scheme of a clock system net (signal lines) on an integrated circuit such as a VLSI is improved so that a delay or a skew of a signal from the signal supplying source to each of the elements is optimized.
Further, the present invention relates to a method of designing a circuit and a recording medium having stored therein a program for designing suitable for use in an implementation design of clock paths of an integrated circuit such as an LSI.
BACKGROUND ART
In general, an integrated circuit such as a VLSI has placed a number of driven elements (e.g., flip-flop cells (sometimes referred to as FF)) which are to be driven synchronously in response to a clock signal. The driven elements are supplied with a clock signal through a clock signal line from a clock supplying source (source).
In this case, as shown in
FIG. 47
, if several ten thousands of FF
502
are connected to a single clock supplying source
501
, it will be impossible for all of the elements to be directly driven by the clock supplying source due to a fan-out restriction. In this case, the term fan-out restriction means a condition which shall be satisfied when a driving element (clock supplying source
501
) drives driven elements (FF
502
) connected to the output side of the driving element. In more concretely, if the driving element does not satisfies the following equation in its driving capability, the elements under deriving cannot be driven.
[driving capability of the driving element]>[wiring capacity from the driving element to driven elements on the next stage]+[load of the driven elements on the next stage]
As described above, if several ten thousands of FFs
502
are arranged to driven directly by a single clock supplying source
1
, the sum of the wiring capacity and loads of the FFs
502
will become extremely large. For this reason, even if a clock signal has a rising edge which rises as shown in
FIG. 48A
upon generating from the clock signal supplying source, the clock signal will come to have a rising edge dull as shown in
FIG. 48B
when the clock signal has traveled the distance from the clock supplying source
501
to each of the FFs
502
, with the result that the clock signal becomes incapable of driving each FF
502
.
For this reason, in general, an arrangement of buffering has been made as shown in FIG.
49
. That is, clock signal lines extending between the clock supplying source
501
to each of the FFs
502
are wired in a tree-like manner (clock tree is synthesized), and a plurality of stages (in the case of
FIG. 49
, a couple of stages are shown) of buffer elements (sometimes referred to as buffer cell) are inserted and placed in the clock signal lines. If such a buffering is effected, the fan-out restriction will be satisfied in each of the plurality of stages of the buffer elements
503
between the clock supplying source
501
to the plurality of FFs
502
.
Further, in order to satisfy the fan-out restriction, taken is a measure known as a buffer-sizing in which each cell provided in a clock system is adjusted or changed in its driving capability. A cell as a target of the buffer-sizing is, in addition to a logic gate or a selector, a buffer element which is provided on a clock signal line as a buffering element as described above. The selector is utilized for selecting a clock signal when a plurality of clock signals are supplied in the circuit under designing.
According to a conventional method of buffering or buffer-sizing, when clock system nets (clock signal lines or clock tree) are synthesized upon designing a circuit, an initial logic is once reduced into a placement based on a netlist obtained by a logic design, and thereafter a portion included in the placement in which the fan-out restriction is not satisfied is subjected to a process of buffering or buffer-sizing so that the portion satisfies the fan-out restriction. If a portion of the placement reduced from the initial logic satisfies the fan-out restriction, the portion is not subjected to the process of buffering or buffer-sizing.
The above-described design scheme is disclosed in, for example, a reference entitled “A Methodology and Algorithms for Post-Placement Delay Optimization” at page 327 to 332 of Proceeding of the 31
st
ACM/IEEE Design Automation Conference written by Lalgudi N. Kannan, Peter R. Suaris, and Hong-Gee Fang.
Recently, an integrated circuit such as a VLSI comes to have a great number of circuit components and hence it is fabricated in a complicated fashion owing to the progress of fabrication technology. With this tendency of technology, a number of elements supplied with a clock signal on the integrated circuit tends to increase, leading to difficulty in designing a clock logic of the integrated circuit.
Further, since a gate is subjected to a microfabrication technology, the integrated circuit device is further requested to process a signal at a higher speed. Thus, it is desired to establish a technology which makes it possible to synthesize a clock tree with a skew reduced. That is, it is desired for the clock signal to reach all driven elements (such as FFs) from a clock supplying source substantially at the same time (ideally exactly at the same time). A scattering of time (of delay) it takes for the clock signal to be transmitted from the clock supplying source to each of the driven elements is known as a clock skew. As described above, as a clock frequency is increased in accordance with the request for the high speed processing, the clock skew is requested to be substantially completely eliminated.
However, as described above, according to the conventional way of buffering, the buffering is carried out only to satisfy the fan-out restriction. Therefore, to reduce the skew by arranging the clock tree in a balanced manner is not taken into account. That is, although the net is subjected to the buffering in such a manner that the driven elements (such as FF elements) are divided into groups so that each of the groups can be driven by a single buffer element, the conventional way of group dividing is effected only to satisfy the fan-out restriction. Therefore, the number of driven elements or the size of load capacity in each group is not taken into consideration. If scattering in the number of elements or load capacity for every group is large, then scattering of wire length from the final stage buffer element to the driven element in each group also becomes large, with the result that it becomes very difficult to adjust the clock skew. Accordingly, in order to satisfy the request of high speed processing, or reduction of the clock skew, which becomes more demanding in recent years, the clock distributing system for distributing the clock to each group shall be arranged in a balanced fashion so as to suppress the scattering in number of elements or the load capacity of every group.
Further, according to the conventional way of buffering, the buffering is not effected in connection with layout information (physical information). Therefore, a layout can result in that a single buffer element is obliged to drive a plurality of flip-flop elements which are remote from the buffer element in terms of physical distance. As a result, there is a fear that a skew adjustment becomes difficult upon arranging layout or that the clock signal line becomes long, which facts lead deterioration in circuit quality.
The pre
Sano Masahiro
Sugioka Toshiaki
Fujitsu Limited
Niebling John F.
Staas & Halsey , LLP
Whitmore Stacy
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