Method of optimizing sidewall spacer size for silicide...

Details Method of optimizing sidewall spacer size for silicide... Method of optimizing sidewall spacer size for silicide...

2008-05-19

2010-06-29

Everhart, Caridad M (Department: 2895)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S704000, C257SE21224, C257SE21226, C257SE21256

Reexamination Certificate

active

07745337

ABSTRACT:
A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

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