Method of optimizing RTL code for multiplex structures

Details Method of optimizing RTL code for multiplex structures Method of optimizing RTL code for multiplex structures

2006-08-01

2006-08-01

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07086015

ABSTRACT:
A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.

REFERENCES:
patent: 6438735 (2002-08-01), McElvain et al.
patent: 2003/0149954 (2003-08-01), McElvain et al.
patent: 2005/0268258 (2005-12-01), Decker

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