Method of optimizing performance of multi-core chips and...

Details Method of optimizing performance of multi-core chips and... Method of optimizing performance of multi-core chips and...

2011-03-29

2011-03-29

Tran, Vincent T (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S002000, C713S100000, C713S321000, C713S322000, C713S330000, C702S118000

Reexamination Certificate

active

07917785

ABSTRACT:
A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.

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“Method and System for Digital Frequency Clocking in Processor Cores”, U.S. Appl. No. 11/734,375, filed Apr. 12, 2007.

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