Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-14
2004-03-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06711720
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the design of CMOS integrated circuits. In particular, the invention relates to automatic resizing of devices and selective substitution of low-threshold devices into CMOS circuits to optimize speed, circuit capacitance and power dissipation.
BACKGROUND OF THE INVENTION
Many CMOS processes involve threshold adjustment implant steps. These threshold adjustment implants typically involve masking operations, such that the N and P type device thresholds may be independently adjusted.
It is known that N-type devices having reduced thresholds may be fabricated by selectively blocking part of the N-type threshold adjustment implant while fabricating N type devices. Similarly, reduced threshold P-type devices may also be fabricated.
A particular example process provides transistors having gate lengths of about a tenth micron, nominal N-type threshold voltages of about 0.3 V for a low threshold Reduced-Vt transistor, and about 0.35 V for a normal threshold transistor. This process also provides P-type Reduced-Vt devices having a threshold of about −0.31 V and normal threshold P-type devices having threshold voltage of about −0.365 V.
On the example process, saturation currents of the Reduced Vt devices tend to be about twenty percent higher than normal threshold devices.
Enhancement, Reduced-Vt, and intrinsic device types are often used together in the design of analog circuitry and special-purpose digital circuitry. For example, a Reduced-Vt device used as a source-follower offers slightly better headroom than an Enhancement device; and a Reduced-Vt device requires less bias voltage than an Enhancement device when used as a capacitor. An N-type Reduced-Vt device source-follower may also be used in parallel with the P-type pullup of a digital clock-driver.
Typical digital signal levels can not be guaranteed to completely turn off typical Reduced-Vt devices; in effect these devices leak more than their normal Vt counterparts.
On the example process, device leakage of the Reduced Vt devices is about ten times higher than that of normal threshold devices, and may reach or exceed two microamps per micron of gate width at high temperatures. This can produce substantial leakage current if a large percentage of transistors on a large integrated circuit, such as a modern processor integrated circuit, are of the Reduced-Vt type.
Gates built of Reduced-Vt transistors can therefore be referred to as a fast-but-leaky gate type, and those of standard thresholds as slow-but-not-leaky gate type.
It is known that the effective source-drain resistance of a CMOS transistor used as a switching device in a logic gate is strongly dependent upon the difference between its gate-source voltage and its threshold voltage
An N-type enhancement pulldown transistor having one volt gate-source will therefore conduct significantly less current than an N-Type Reduced-Vt device of the same size and having the same gate-source voltage. On an example process, this current may be twenty percent higher for Reduced-Vt devices than for normal devices. For this reason, Reduced-Vt devices have been used in speed-critical logic circuits where timing requirements can be met in no other way.
Threshold voltage can also be effectively increased, and leakage substantially reduced, by increasing device length, with consequence of increased gate capacitance and reduced IDSat (hence reduced speed). Even a small increase in length can substantially reduce leakage. A CMOS design may use gates with normal L's for speed where necessary, and gates with slightly greater L's where lower leakage is important. The normal L devices may also be termed a fast-but-leaky type and the greater L devices as slow-but-not-leaky type. For example, Transistors on a 0.1 u process could have 0.1 u L when high speed is needed, while they could be ten percent longer when lower leakage outweighs the speed disadvantage.
It is also known that effective threshold voltage of MOS transistors in logic circuits may be adjusted by applying substrate or well bias. Variation in threshold with substrate bias is known as the body effect. For n-channel transistors, the conventional substrate bias is 0 V, and for p-channel transistors the conventional bias is the local power supply voltage VDD. If the N type bias is increased to a level above circuit ground, Vt can be reduced a little at the expense of increased junction capacitance. Similarly, if N type bias is decreased to a level below circuit ground, Vt can be effectively increased and junction capacitance decreased. P-channel transistors are similarly affected, although polarity is reversed.
Standard CMOS N-well processes lend themselves readily to application of bias to wells, and thereby to P-type transistors. Other processes may be adaptable to application of bias to N-type transistors. For purposes of this patent, devices having transistors with bias such that the absolute value of threshold voltage is reduced are also termed a fast-but-leaky type and devices with a bias such that the absolute value of threshold voltage is increase are termed a slow-but-not-leaky type.
Power dissipated in CMOS integrated circuits is often described as having a static component and a dynamic component. Static power includes power dissipated through junction and device leakage, power dissipated through resistive and current-source loads, and other power consumption that is not a function of switching activity.
Dynamic power includes power dissipated through charging and discharging capacitances, including gate capacitances, as well as crossover current dissipated during signal transitions at gate inputs. Crossover current includes current that passes from rail to rail through both the N-type and P-type stacks of a CMOS gate because both stacks are partially conductive during a transition of an input signal to the gate. Dynamic power is generally a function of parameters including the clock rate, the capacitance switched by devices, and the supply voltage.
Historically, the component of dynamic power associated with charging and discharging capacitances has been more significant than that associated with crossover current. This was because transistors in CMOS circuits historically transition from the off-state to the on-state and vice versa rather than transitioning between a partially-conductive state and the fully on-state. The component of dynamic power associated with crossover current has generally been ignored in the design of integrated circuits.
The component of dynamic power associated with charging and discharging capacitances is proportional to the product of capacitance times the charge and discharge rate times the square of the voltage. The activity ratio of each node is the ratio of the charge and discharge rate of the node to the clock rate. Dynamic power is therefore generally proportional to the product of clock rate times the activity ratio times node capacitance times the square of the power supply voltage.
The activity ratios of nodes of a processor or other large logic circuit vary with the design of the circuit, the position in the circuit of the nodes, and with the functional environment of the circuit. The activity ratios of different nodes in a circuit may vary substantially. The functional environment of the circuit includes, for processor circuits, code running on the processor.
The total power dissipated by a device includes both static power and dynamic power. Leakage in Reduced-Vt devices used in logic gates contributes to static power.
Much design of complex integrated circuits is accomplished through a design flow that begins with creation of a synthesizable register-transfer-level (RTL) description of the circuit. Synthesis tools, available from Cadence Design, Mentor Graphics, and Synopsys, among other vendors, map this RTL description into a gate-level netlist. Selected circuitry may also be synthesized manually through creation of gate-level schematics and extraction of the schematics to create a gate-level netlist. Static timing
Hewlett--Packard Development Company, L.P.
Siek Vuthe
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