Method of optimizing critical path delay in an integrated...

Details Method of optimizing critical path delay in an integrated... Method of optimizing critical path delay in an integrated...

2007-02-20

2007-02-20

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10975981

ABSTRACT:
A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.

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