Method of optimization of CPU and chipset performance by...

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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C712S300000

Reexamination Certificate

active

07051195

ABSTRACT:
In processing an instruction request, the invention determines whether the request is speculative or not based upon a bit field within the instruction. If the request is speculative, bus congestion and/or target memory is assessed for conditions and a decision is made, based on the conditions, as to whether or not to process the request. To facilitate the invention, certain bit fields within the instruction are encoded to identify the request as speculative or not. Additional bit fields may define a priority of a speculative request to influence the decision to process as based on the conditions. CPU architectures incorporating prefetch logic may be modified to recognize instructions encoded with speculation and priority identification fields to implement the invention in existing systems. Other logic, e.g., bus controllers and switches, may similarly process speculative requests to enhance system performance.

REFERENCES:
patent: 5694574 (1997-12-01), Abramson et al.
patent: 5892936 (1999-04-01), Tran et al.
patent: 6567901 (2003-05-01), Neufeld
patent: 6654860 (2003-11-01), Strongin et al.

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