Method of optimization of clock gating in integrated circuit...

Details Method of optimization of clock gating in integrated circuit... Method of optimization of clock gating in integrated circuit...

2006-05-22

2009-06-09

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S014000, C703S019000

Reexamination Certificate

active

07546559

ABSTRACT:
A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for identifying registers that are candidates for clock gating is presented. Furthermore, a determination is made regarding which of the candidate registers to clock gate in order to achieve optimal power and IC area savings. The determination is based on switching activity of the candidate registers.

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