Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent
1990-06-29
1991-10-08
Gossage, Glenn
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
365185, 365194, 36523006, 307449, 307482, 307578, G11C 1606
Patent
active
050560620
ABSTRACT:
A method of operating an EPROM which has a word line, a predecode circuit having an ou tput terminal and a transistor having a first electrode connected to the output terminal of the predecode circuit, a second electrode connected to a word line and a control gate. The method of operating the EPROM includes generating a selection signal and an inverted signal thereof in accordance with an internal address signal, and generating a delayed signal responsive to the selection signal and the inverted signal so that the delayed signal rises by a predetermined time delay behind a rising of the selection signal and rapidly falls substantially simultaneously with a rising of the inverted signal. Thereafter the potential of the selection signal is boosted in accordance with a potential of the delayed signal and the boosted selection signal is supplied to the control gate of the transistor connected between the predecode circuit and the word line.
REFERENCES:
patent: 4622479 (1986-11-01), Taylor
patent: 4649521 (1987-03-01), Tsuchida et al.
patent: 4704706 (1987-11-01), Nakano et al.
patent: 4806798 (1989-02-01), Kanauchi
patent: 4811292 (1989-03-01), Watanabe
patent: 4814647 (1989-03-01), Tran
Kitazawa Shooji
Kuwabara Hiroshi
Gossage Glenn
OKI Electric Industry Co., Ltd.
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