Method of operating a synchronous memory device having a variabl

Details Method of operating a synchronous memory device having a variabl Method of operating a synchronous memory device having a variabl

1999-02-19

2000-02-29

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 35, G06F 1300

Patent

active

060322144

ABSTRACT:
The present invention is directed to a method of operating a memory device wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to a first external clock signal and a second external clock signal. In one preferred embodiment, the method may further include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory device. In this preferred embodiment, the first amount of data corresponding to the first block size information is output after the number of clock cycles of the first and second external clock transpire. The number of clock cycles may be a whole number or a fraction.

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