Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-08-17
2003-07-15
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06594731
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of operating a storage system comprising a main memory and a cache memory structured in address-related lines, in which cache memory can be loaded with data from the main memory and be read out by a processor as required. During the access of the processor to data of a certain address in the cache memory, at which address certain data from the main memory which has a corresponding address is stored, a test is made to determine whether sequential data is stored at the next address in the cache memory; and this sequential data, if unavailable, can be loaded from the main memory in the cache memory via a prefetch.
In known storage systems, a plurality of data stored in the main memory are loaded in a cache memory already prior to their being called by an assigned processor, which runs a respective program. A cache memory is a high-speed buffer memory from which the necessary data is made available to the processor in a considerably faster way than from the main memory, which operates much more slowly. To ensure that in most cases the data required by the processor is available in the cache memory, the prefetch has come to be used. In the case of a prefetch operation, data which is not yet required by the processor for the moment, but which will probably shortly be required based on the processor access to the cache memory, has already previously been loaded from the main memory into the cache memory or a register, so that it is then available when the processor needs this data. A cache memory is subdivided into a plurality of lines which are typically also structured in columns, and each cache memory line is assigned a certain address line. In each line of the cache memory, a line of the main memory is written, and the line address of the cache memory corresponds to that of the main memory. Each line thus written has a certain length over. The mode of operation of such a storage system is such that when a hit occurs in the cache line N, which contains the data of the main memory address A, simultaneously a test is made to determine whether the data of the address <A plus line length> is available in the cache line N+1. Thus, assuming a hit in the cache line N, a check is invariably made whether the next line contains sequential data which the processor will probably need shortly. If this is not the case, a prefetch operation follows in which the data of the address <A plus line length> is loaded either in the cache memory or in an assigned register.
Basically, the use of prefetch for a cache memory increases the hit rate in the cache memory achieved by the processor. A high hit rate in its turn leads to a better performance of the system, because the memory access can be carried out without delay in case of a hit, whereas a miss leads to an access to the slower main memory and decelerates the system.
As a result of the use of prefetch, there are also disadvantages. Data is loaded from the main memory in the cache memory that may not be needed at all. This hazard particularly exists in the case of large line lengths that cause a large amount of data to be transmitted to the cache memory during a prefetch operation. Since each data transfer increases power consumption, power loss increases. Moreover, a conflict arises when during a prefetch operation a miss happens in the cache memory (the processor does not find the desired data there). The prefetch operation must then be either aborted or terminated before the necessary data can be loaded. In both cases additional delays arise, which reduce the efficiency of the system.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of operating a storage system that improves the efficiency of the system when a prefetch strategy is used and that reduces power consumption.
To solve this problem, a method is provided wherein a prefetch only takes place when the processor accesses a predefined line section that lies within a line.
During the test of whether sequential data is available, only if it is missing will a prefetch be carried out. Advantageously, according to the invention, a prefetch operation is not initiated until the processor accesses data that lies in a predefined line section within a line. The prefetch is based on the recognition that the probability that the data of the line sequentially following the processed line is needed by the processor is proportionally greater the further away in the line N the hit lies, or that the processor reads out data. Then the assumption is strengthened that the processor that reads out the data of the line N will shortly need the sequential data of the next line N+1 as it is stored in the main memory. As a result of the definition of a certain line section, which defines the part of a line which the processor is to access for a prefetch operation to actually occur, the above probability can be taken into account. If the processor accesses an address in the line that lies outside the predefined line section, a prefetch cannot (yet) be initiated.
As a result, the efficiency of the system can be enhanced, because a prefetch operation is not initiated until it is highly likely that the data fetched from the main memory is also really used. A prefetch is thus not automatically carried out each time it is established that the sequential data is not available, but only in preferred cases. This lowers the number of prefetch operations carried out during a program run, leading to a drop in power consumption, which is caused by the loading of data in the cache memory or its associated register. In contrast to a conventional prefetch strategy, the power consumption for the data transfer may be lowered by more than 30% because of improved system efficiency. A specially preferred application of this prefetch strategy lies in the area of mobile radio telephony, i.e., when the storage system is used in a mobile radio telephony terminal.
For simplicity, the line section can be defined in accordance with the invention by a predetermined line section address and can contain all the addresses of a line that are larger than or equal to the line section address. The address within the line which the processor has access to is compared to the line section address so as to establish via this comparison whether the processor now works within or without the predefined line section, so that a decision can be made whether a prefetch can be initiated or not. The placement or selection of the line section address ultimately depends on the power parameters of the processor (e.g., the processor clock and the rate of the transmission of data from the main memory), but also on the structure of the program which is run by the processor. In particular, the structure of the program determines whether the processor continuously processes the data—in essence, line-address by line-address or line by line—or whether during the running of the program there are many line jumps. Basically, the line section address is to be positioned so that in the majority of cases the prefetch operation has already been terminated before the data is accessed by the processor.
Each line of the cache memory can be subdivided into a plurality of line areas of a certain length, each of which is assigned its own line area address, and the line area address is then compared to the line section address. This takes into account the possibility of configuring a cache memory in various forms, one of which is the subdivision of each cache memory line or of the whole cache memory into a plurality of columns, the columns having different lengths depending on the cache memory configuration. In each line area can be written a certain amount of data which can be retrieved with the aid of the line area address, which is compared to the line section address to test the “type of job” of the processor within the line. The line section address can be given in the form of a number value, and a comparative value is determined on the basis of the line sect
Bauer Harald
Fawer Urs
Hertwig Axel
Lippens Paul
Bragdon Reginald G.
Inoa Midys
Koninklijke Philips Electronics , N.V.
Le Pennec Gwennelle
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