Method of operating a semiconductor memory device

Details Method of operating a semiconductor memory device Method of operating a semiconductor memory device

1991-01-18

1993-10-05

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365228, 365218, 365182, 257296, 257314, 257908, G11C 1140

Patent

active

052511715

ABSTRACT:
A method which can operate a semiconductor memory device having a volatile memory and a non-volatile memory without lowering the retention characteristic of the non-volatile memory is described. The volatile memory includes a MOS transistor, and a capacitor, one electrode of which is connected to the source of the MOS transistor. The non-volatile memory includes a floating gate transistor. The semiconductor memory device further has a switch connected between the source of the MOS transistor and the drain of the floating gate transistor. The control gate of the floating gate transistor is connected to the source of the MOS transistor. When the switch is off and the volatile memory to be operated, a voltage which is substantially one half of that of a power source voltage with respect to the ground level is applied to the source of the floating gate transistor.

REFERENCES:
patent: 4903236 (1990-02-01), Nakayama et al.
patent: 5043946 (1991-08-01), Yamauchi et al.
Yamauchi et al., IEDM 88:416-419.
Yamauchi et al., IEDM 89:595-598.
U.S. Patent Application Ser. No. 07/549,293 (filed Jul. 6, 1990).

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