Method of operand width reduction to enable usage of...

Details Method of operand width reduction to enable usage of... Method of operand width reduction to enable usage of...

2011-06-14

2011-06-14

Bullock, Jr., Lewis A (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S550000, C708S700000

Reexamination Certificate

active

07962538

ABSTRACT:
An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N. To enable a wider re-usage of existing designs or building blocks being all specialized to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimized in regard of speed and space savings, a circuit is implemented as an addend width reduction circuit to perform the steps of: receiving said two N-bit operands as an input, adding the (N−M+1) most significant bits of said two N-bit operands separately in an auxiliary adder logic, calculating at least the two most significant bits of reduced-bit-length output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined post-processing can be correctly performed with said output operands.

REFERENCES:
patent: 4819198 (1989-04-01), Noll et al.
patent: 5623423 (1997-04-01), Lipovski
patent: 5835782 (1998-11-01), Lin et al.
patent: 6732126 (2004-05-01), Wang

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