Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2002-03-21
2003-06-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C257S529000
Reexamination Certificate
active
06573125
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of opening a repair fuse of a semiconductor device.
2. Description of the Related Art
Semiconductor memory devices have been continuously developed toward being highly integrated and having large capacity, due to great advances in material technology and thin-layer technology, as well as photolithography, new memory cell structures, transistor technology and circuit technology. In particular, as a DRAM cell is scaled down, it is very important to secure a capacitor capacity required for reading and writing data. Two types of three-dimensional capacitors have been designed to solve this problem, i.e., a stack structure of a capacitor-over-bit-line (COB) and a trench structure of a capacitor-under-bit-line (CUB). At present, the stack structure of the COB is widely used.
A reduction in the size of a semiconductor device results in an increase in the height of a capacitor of a three-dimensional DRAM cell of a stack structure, because a sufficient capacitor capacity must be secured for stable operation in the DRAM cell. Generally, the height of a capacitor is required to be more than 1 &mgr;m in the case of a highly integrated device such as a 256M-DRAM.
Also, when a general semiconductor device including a semiconductor memory device has a circuit which does not operate due to defects occurring during a manufacturing process, a repair process in which a defective circuit is replaced with an extra circuit or a trimming process in which the characteristics of a circuit are changed to be compatible with the semiconductor memory device, is performed. During the repair process and the trimming process, replacement of a circuit or change of the circuit characteristics is performed by cutting a portion of a predetermined connection of the circuit by irradiating a laser thereon. The connection which is cut by laser is called a ‘fuse line’ and a portion of the connection to be cut and a region encircling the portion are called a ‘fuse region’. In a semiconductor device, a fuse is usually used for repairing a memory cell through the repair process. A defective cell is replaced with a redundant cell by using a laser beam or the like to cut a fuse of a redundancy decoder corresponding to an address of a main cell to be replaced.
Due to the high integration of a semiconductor memory device, a large number of redundant cells and fuses are needed for repairing the defective cells. As a result, the width and pitch of fuses is getting narrower, which requires a more precise manufacturing process. That is, a fuse corresponding to a defective cell must be accurately aligned and cut.
However, as the height of a capacitor increases, the capacitor must be etched at least up to 3 &mgr;m in order to completely open a repair fuse. For this reason, there are a lot of cases where a fuse line is not completely open or a fuse line is attacked during the etching process used to open the fuse line.
FIGS. 1 through 7
are cross-sectional views illustrating a conventional method for opening a repair fuse of a semiconductor device.
Referring to
FIG. 1
, a cell region (a) and a peripheral circuit region (b) and a fuse region (c) are defined in a semiconductor substrate
100
. A field oxide layer
102
is formed in each of the regions (a) to (c) to electrically separate active regions in regions (a) to (c) of the semiconductor substrate
100
.
Next, transistors made of a source
104
, a drain
104
and a gate electrode
112
are formed in the cell region (a) and the peripheral circuit region (b). The gate electrode
112
is formed with a gate oxide layer
106
, a gate-conductive layer
108
and a capping dielectric layer
110
, and has a spacer
114
along its sidewalls.
Then, a first interlevel dielectric layer
115
is deposited on the semiconductor substrate
100
having the above transistors, and then is planarized through a chemical mechanical polishing (CMP).
Thereafter, the first interlevel dielectric layer
115
is patterned to form a contact pad
116
which is electrically connected to the source/drain region
104
. Then, a conductive material is filled in the interlevel dielectric layer
115
and planarized through the CMP. In the cell region (a), nodes are separated as a result of the above planarizing process and thus, the contact pad
116
connected to the source/drain
104
is formed.
Next, a second interlevel dielectric layer
118
is formed on the entire semiconductor substrate
100
and planarized through the CMP.
A contact hole (not shown) passing through the second interlevel dielectric layer
118
or the second interlevel dielectric layer
118
and the first interlevel dielectric layer
115
is obtained through a general photolithography or etching process. A conductive material is filled into the contact holes, thus forming a contact plug
120
.
Then, a conductive material and a capping dielectric layer are deposited on the second interlevel dielectric layer
118
and patterned, forming a bit line
126
and fuse line
126
. The bit line
126
and fuse line
126
are structures in which a conductive layer
122
and a capping dielectric layer
124
are stacked sequentially and/or a spacer
128
is formed along the sidewalls. The bit line
126
is electrically connected to the contact plug
120
.
A third interlevel dielectric layer
130
is formed on the entire semiconductor substrate
100
having the bit line
126
and the fuse line
126
, and then is planarized through the CMP.
Next, a contact hole which passes through the second and third interlevel dielectric layers
118
and
130
is formed through a general photolithography and etching process and filled with a conductive material. As a result, a contact plug
132
is formed, which is electrically connected to the contact pad
116
.
A capacitor
140
made of a lower electrode
134
, a dielectric layer
136
and an upper plate electrode
138
is formed on the third interlevel dielectric layer
130
and the contact plug
132
. The lower electrode
134
is electrically connected to the contact plug
132
.
Referring to
FIG. 2
, a fourth interlevel dielectric layer
142
is deposited on the entire semiconductor substrate
100
.
Referring to
FIG. 3
, a fourth interlevel dielectric layer
142
is planarized through the CMP. The thickness of the planarized fourth interlevel dielectric layer
142
a
is higher than the height of the capacitor
140
.
Referring to
FIG. 4
, a contact hole is formed on the semiconductor substrate
100
through a general photolithography and etching process and filled with a conductive material thereby forming a metal contact
144
.
Next, a conductive material is deposited on the fourth interlevel dielectric layer
142
a
and the metal contact
144
and patterned through a general photolithography and etching process, thereby forming a first metal interconnection layer
146
. The first metal interconnection layer
146
is electrically connected to the metal contact
144
.
Referring to
FIG. 5
, an intermetallic dielectric layer
148
is formed on the entire semiconductor substrate
100
on which the first metal interconnection layer
146
is formed.
Next, a via hole connected with the first metal interconnection layer
146
is obtained through a general photolithography and etching process and filled with a conductive material, thereby forming a via contact
150
.
Thereafter, a conductive material is deposited on the via contact
150
and the intermetallic dielectric layer
148
and patterned through the general photolithography and etching process, thereby forming a second metal interconnection layer
152
which is electrically connected to the via contact
150
.
Referring to
FIG. 6
, a passivation oxide layer
154
and a passivation nitride layer
156
are sequentially formed on the entire semiconductor substrate
100
.
Referring to
FIG. 7
, a fuse opening process is performed using the photolithography and etching process. Specifically, the passi
Hoang Quoc
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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