Method of on-chip interconnect design

Details Method of on-chip interconnect design Method of on-chip interconnect design

1998-10-02

2001-08-21

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S013000

Reexamination Certificate

active

06279142

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to integrated circuit fabrication methods, and in particular, to early-stage design of on-chip interconnects to reduce on-chip signal coupled noise and signal transition rate degradation.
BACKGROUND INFORMATION
Continued advances in silicon complementary metal oxide semiconductor (CMOS) technologies have yielded significant increases in both circuit speed and wiring density. These improvements have resulted from reductions in device physical parameters, wire physical dimensions and power supply voltages. As a result of scaling to sub-micron dimensions, a significant proportion of propagation delays are transferred from the logic gates to the on-chip interconnecting wires due to the increase in serial RC effects. This causes a degradation of the transition, or slew rate, of the driving signal, resulting in additional net delay.
Furthermore, the scaling has led to wire geometries with aspect ratios (thickness/width) greater than one. The increased aspect ratios along with the reduction in conductor spacings resulting from the scaling to smaller dimensions gives rise to increased coupling capacitance to neighboring wires. This increases signal coupled noise to nearby nets. In addition, lower power supply voltages reduce the noise margin of logical circuits, making chip functionality more sensitive to interconnect parasitic effects.
As a consequence, data integrity issues are exacerbated as integrated circuit sizes are reduced. These issues include false switch or latch disturb problems due to excessive line to line noise coupling. The influence of adjacent lines switching, in conjunction with poor transition rates in the target net, can create a significant delay variation or noise jitter which can be detrimental to chip functionality, performance and reliability. In fabrication methodologies according to the prior art, these are typically resolved in post-route noise and jitter checks. For nets that failed to conform to noise and slew rate specification, iterating post-route designs to bring the offending networks into conformance with the specifications is costly.
Although methods of pre-route design have been used in the art, these have been limited in their effectiveness. A wire rule based approach has been used to address noise and slew rate criteria in the pre-route phase of IC design. See, Howard Smith and Noises Cases, “Wire Rule Methodology for On-Chip Interconnects,” IEEE EPEP 96, pp. 33-35, October 1996. This methodology admits only a single net length. Thus, noise margin and slew rate designs using this methodology relies on a simple “averaged” receiver position to represent each receiver in the net.
Therefore, there is a need in the art for a design methodology that reduces the need for post-route design iterations. Such a methodology would address on-chip signal coupled noise and slew rate degradation in the early stages of the chip design cycle.
SUMMARY OF THE INVENTION
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a method of integrated circuit (IC) design. The method includes the steps of generating a resistor/capacitor (RC) network for a current net, and assigning a parasitic coupling capacitance and a shunt capacitance to a reference electrode for each network capacitor in the RC network. The capacitances are derived from a three dimensional (3-D) field solution for a preselected wire geometry. These wire geometries are specified as a conductor width and associated minimum spacing to an assumed neighboring net. A first circuit simulation of the current net including the RC network from the assigning step, wherein the first circuit simulation outputs net noise signals generated in response to a noise source.
Additionally, there is provided, in a second form a computer program product on a computer readable medium for IC design. The computer program product includes programming for generating a resistor/capacitor (RC) network for a current net and programming for assigning a parasitic coupling capacitance and a shunt capacitance to a reference electrode for each network capacitor in the RC network.
The capacitances are derived from a three dimensional (3-D) field solution for a preselected wire geometry. Also includes is programming for performing a first circuit simulation of the current net including the RC network from the assigning step, wherein the first fast circuit simulation outputs net noise signals generated in response to a noise source.
There is also provided, in a third form, a data processing system for integrated circuit (IC) design having circuitry operable for generating a resistor/capacitor (RC) network for a current net, and circuitry operable for assigning a parasitic coupling capacitance and a shunt capacitance to a reference electrode for each network capacitor in the RC network, wherein the capacitances are derived from a three dimensional (3-D) field solution for a preselected wire geometry. The data processing system further includes circuitry operable for performing a first circuit simulation of the current net including the RC network from the assigning step, wherein the first fast circuit simulation outputs net noise signals generated in response to a noise source.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


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