Method of obtaining a buffer contiguous memory and building a pa

Details Method of obtaining a buffer contiguous memory and building a pa Method of obtaining a buffer contiguous memory and building a pa

1996-09-30

1999-11-16

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711203, 345515, G06F 1210

Patent

active

059875828

ABSTRACT:
In a computer system, a peripheral graphics device (PGD) accesses a graphics buffer (GB) wherein the GB physical pages can be contiguous or discontiguous. A request is received to allocate memory for a GB of a predetermined size and handle. The number of pages within the size parameter is determined based on the page size used by the computer system and the buffer size needed. A first memory block is allocated for storing the GB and locked to prevent swapping. A starting virtual address of a CPU page table (CPU/PT) is accessed and mapped to a starting logical address to allow traversal of the CPU/PT by a user application. A second memory block is allocated for building a graphics device page table (GDPT) that can be accessed by a PGD. The logical address of each GB page is sequentially accessed and the corresponding physical address of each GB page is determined from the CPU/PT. The logical and physical addresses of each GB page are stored into the GDPT. If all physical pages of the GB are contiguous, the logical and physical addresses of the GB are stored into a database indexed by a user handle. Otherwise, the starting address of the GDPT is stored into the database indexed by a user handle. Provided that all of the GB physical pages are contiguous, the PGD accesses the GB by its starting physical address. Otherwise, the PGD uses the GDPT to access the discontiguous physical pages of the GB.

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U.S. application No. 08/720,396 filed on Sep. 30, 1996 by McDonald et al.
*Based on US APP 08/438,860 filed May 10, 1995.

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