Method of multiplexed address and data bus

Details Method of multiplexed address and data bus Method of multiplexed address and data bus

2001-04-20

2004-11-23

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

C711S153000, C365S189020, C365S230020

Reexamination Certificate

active

06823441

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to a communication architecture for communication between two microprocessors. More particularly, the invention relates to an address/data parallel bus architecture which allows communication between two system on chip (SOC) microprocessors.
2. Discussion
Current production vehicles have a variety of systems which are now controlled by microprocessors. For example, the operation of the vehicle engine is typically controlled by one microprocessor, and the operation of the vehicle transmission is typically controlled by another microprocessor. In some types of vehicles, yet another microprocessor may be used for controlling vehicle systems such as security, navigation, and safety systems such as anti-lock brakes and crash management devices. As the vehicle systems become more complex, it is necessary for the various microprocessors to share commonly used information.
System-on-chip (SOC) microcontroller architecture demands that most functions of an electronic control unit (ECU) be integrated onto one piece of silicon. The result is a SOC ECU digital core that ends up being a very large, complex piece of silicon. These SOC devices also have multi-faceted operational requirements, and thus are usually challenged by a multitude of simultaneous tasks. When adding functionality to these complex ECU's, simplicity of interface to the software is of prime importance.
When multiple ECU digital cores are housed on one physical box, often large amounts of data sharing between the ECU's must be accomplished. Each ECU has its own set of input and output functional requirements to perform its overall tasks. With present requirements these input and output functions translate into a large number of pins on the side of the silicon die as well as a large amount of processing power to handle these inputs and outputs. Sharing of some input/output functions between the digital cores housed in a single box becomes the economical choice to keep pin counts low and to keep processor burden low.
For example, two very large SOC ECU silicon digital cores could be an engine control function and a transmission control function. For optimal performance these two cores must share large amounts of data, and they must do the data sharing in real-time. The delays that are typical of a serial communication link between the ECUs may prohibit certain types of feature development, due to the delays and complexities that are inherent in serial communication links. For quick reliable communications between the two cores, a parallel bus architecture between the cores (which could place data to be communicated between the cores in specific registers for both sides to use) has been discovered to be the most efficient way to accomplish the task.
Accordingly, it is desirable to provide an address/data bus for communicating between two vehicle based microprocessors. It is further desirable to provide an address/data bus with minimized pin count which reduces the effects of electromagnetic interference (EMI). Finally, it is desirable to provide an address/data bus which allows for bus access between microprocessor cores which are running at different system clock speeds.
These and other objects are obtained by providing a multiplexed address and data bus controlled by a bus master for communication between two microprocessors. The multiplexed address and data bus include a plurality of multiplexed address and data lines in communication between the two microprocessors. A read/write control signal line is provided in communication between the two microprocessors for communicating whether a read or a write operation is to be performed. A chip select line is in communication between the two microprocessors, the chip select line transitioning to an enable condition during a data transfer cycle. A data strobe line communicates between the two microprocessors, the data strobe line providing a plurality of signals for each data transfer cycle wherein each data transfer cycle includes a plurality of write and read sequences which are initiated by the signals from the data strobe line.


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