Method of multilevel dram sense and restore

Static information storage and retrieval – Systems using particular element – Capacitors

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365203, G11C 1124

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active

055329551

ABSTRACT:
A method of processing a data bit having one of four voltage levels stored in a dynamic random access memory (DRAM) cell capacitor comprised of sensing whether or not the data bit voltage is above or below a voltage level midway between a highest and a lowest level of the four levels, and indicating a sign bit based thereon, setting a threshold level based on the ratio of the capacitance of a storage cell capacitor and the total of the cell capacitor, a dummy cell capacitor and a bitline and the value of a sign bit, and sensing whether the data voltage is higher or lower than the threshold level, and indicating a magnitude bit based thereon, whereby the combination of the sign and magnitude bits represent which of the four levels is the voltage level data bit.

REFERENCES:
patent: 4771404 (1988-09-01), Mano et al.
patent: 5184324 (1993-02-01), Ohta
patent: 5283761 (1994-02-01), Gillingham
patent: 5293563 (1994-03-01), Ohta
Ohta, Yoshiji et al., Symposium, "A Novel Memory Cell Architecture for High-Density DRAMs," VLSI Circuits, May 1989, pp. 101-102.

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