Static information storage and retrieval – Read/write circuit – Including signal comparison
Reissue Patent
1996-01-31
2001-02-27
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S189090, C365S149000, C365S168000, C365S190000, C327S056000, C327S052000
Reissue Patent
active
RE037072
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to dynamic random access memory (DRAM) memories, and in particular to a method of storing a variable level signal in each cell of a DRAM for representing more than one bit in each cell.
BACKGROUND OF THE INVENTION
To store for example two bits in a DRAM cell, it must be able to store four different voltage levels. A problem with such cells, is that noise margins are reduced to one-third that of a one bit per cell DRAM, which is too low to withstand the occasional &agr;-particle bit.
A second problem with multi-bit storage cells relates to the method of sensing. No simple method of sensing has previously been designed, although attempts have been made to solve this problem, e.g. as described in the publication by M. Aoki, et al, “A 16-Levels/Cell Dynamic Memory”, ISSCC Dig. TECH. Papers 1985, pp. 246-247, and in T. Furuyama et al, “An Experimental Two-Bit/Cell Storage DRAM for Macrocell or Memory-On-Application”, IEEE Journal of Solid State Circuits, Vol. 24, No. 2, pp. 388-393, April 1989. The technique described by Aoki cannot use normal sense amplifiers. It requires a precision analog D to A converter to implement a staircase waveform and a charge amplifier to sense data. The technique described by Furuyama requires the generation of precision reference levels to distinguish between four levels. These levels are not self-compensated for offsets developed in the sensing operation, and this method suffers from poor signal margin. Hidaka et al describe a technique for simultaneously reading two cells at a time in the article “A divided/Shared Bitline Sensing Scheme for 64Mb DRAM Core” in the 1990 Symposium on VLSI Circuitry 1990, IEEE, p,. 15, 16 which while describing dividing a bitline, is not related to multiple bit storage in a single cell.
DRAMs have previously been built with cells holding up to sixteen bits of storage, e.g. in the aforenoted article by M. Aoki et al, for use in file memories. A 4 K test array is believed to have been the largest memory built using this design. Leakage characteristics of the DRAM cell were required to be very tightly controlled and even then, accurate sensing of the small voltage differences between levels becomes very difficult. Another problem with this scheme was the length of time required to access: a single read cycle required 16 clocks for the read followed by 16 clocks for the restore.
To implement a 2 bit DRAM, one can define the cell as storing one of four voltage levels V
cell0
, V
cell1
, V
cell2
and V
cell3
, and reference voltage midpoints between these four voltage, which can be defined as V
ref1
, V
ref2
and V
ref3
. These midpoints can be referred to, to differentiate between the four voltage levels. The relative voltage of these levels are shown in Table 1 below.
STORAGE
REFERENCE
ACTUAL
VOLTAGES
VOLTAGES
VOLTAGE
V
cell1
V
DD
V
ref3
5/6 V
DD
V
cell2
2/3 V
DD
V
ref2
1/2 V
DD
V
cell1
1/3 V
DD
V
ref1
1/6 V
DD
V
cell0
V
SS
The storage voltages are the actual voltages stored in the cells, although the sensing voltages are somewhat more attenuated. Since sensing takes place on the bitlines which divide cell charge by the cell to bitline capacitance ratio, much lower voltages than those in the cell are actually sensed. In a standard DRAM, these voltage differences are in the order of 100-300 mV. It is the voltage midpoints between these smaller signals that must finally be generated to allow for correct sensing.
Furuyama et al in the article noted above describes one method of sensing these voltages. Furuyama et al used three sense amplifiers and three approximate midpoint sensing voltages. The cell charge is shared with the bitline, the bitline is split into three sections (sub-bitlines) and three sense amplifiers determine whether the cell charge is above or below their particular reference voltages. This data is then converted to two bits and a resulting output. Reconversion of the two bits allows approximate values to be driven into the bitlines so that restore takes place after the read cycle. A write cycle operates in the same way as the restore section of the read cycle.
It should be noted that since the cell shares charge with three sub-bitlines, and the reference cell with only one sub-bitline, the reference voltage is about three times larger than it should be for sensing, casting doubt on the operability of this design. Secondly, three sense amplifiers are used, and since sense amplifiers have been growing proportionally larger and larger with each generation of memory, a minimum of sense amplifiers is desirable. A third problem is that the reference voltage is
not
stored on a cell whose
leakage does not
characteristics
track the leakage of the data cells, introducing another source of error into the circuit.
SUMMARY OF THE PRESENT INVENTION
In the present invention a method and circuit has been designed which substantially solves
some of
the above-identified problems. Only two sense amplifiers are required
, which generate the sensing voltages at the time of sensing
. In the present invention each bitline is split exactly in half, rather than into thirds, by use of a switch. The
noise margins are relatively large, equivalent to that of a standard DRAM maintaining reliability, and the
present design can be used as a standard one bit per cell DRAM as an alternative to a multiple bit per cell DRAM, which increases its universality, allows it to be used in present designs, and increases yield.
In accordance with an embodiment of the present invention, a method of processing data having one of four levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower in voltage than the reference line, whereby which of the four levels the data bit occupies is read.
In accordance with an embodiment of the present invention, a method of processing data having one of plural levels stored in a DRAM cell capacitor is comprised of dumping the charge of the cell capacitor on a first of a pair of conductors of a folded bitline, maintaining the other of the pair of conductors split into other sub-bitline conductors and charging each of the other sub-bitline conductors to an intermediate voltage, splitting the first of the conductors into first sub-bitline conductors, sensing the sub-bitlines to determine whether the charge of the cell has a higher voltage than the intermediate voltage of one of the other sub-bitline conductors and providing a logic level result signal, storing the logic level result signal in a dummy cell capacitor, setting a charge storage capacitor and all of the sub-bitlines other than the first sub-bitline maintaining a voltage resulting from the dumped charge to a predetermined voltage, dumping charge stored in the dummy cell capacitor on the sub-bitlines and charge storage capacitor, thereby varying the predetermined voltage stored thereon to a degree related to the capacities of the dummy cell capacitor, the charge storage cells and the predetermined voltage, to a level above or below the intermediate level, isolating the sub-bitlines, applying the intermediate voltage to one of the other sub-bitline conductors, comparing the cell voltage on one sub-bitline with the voltage on the other sub-bitline carrying the level above or below the intermediate level to obtain a first logic bit, and comparing the voltages carried by the other sub-bitlines to obtain a second logic bit, whereby the first and second logic bits are indicative of one of four logic states corresponding to one of the plural levels stored in the DRAM cell.
REFERENCES:
paten
Hamilton, Brook, Smith & Reynolds, P.C
Mosaid Technologies Inc.
Tran Andrew Q.
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