Method of multi-level storage in DRAM

Details Method of multi-level storage in DRAM Method of multi-level storage in DRAM

1992-07-22

1994-02-01

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Including signal comparison

36518909, 365149, 3652335, 365168, 307530, G11C 700

Patent

active

052837610

ABSTRACT:
A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.

REFERENCES:
patent: 4287570 (1981-09-01), Stark
patent: 4415992 (1983-11-01), Adlhoch
patent: 4661929 (1987-04-01), Aoki et al.
patent: 4771404 (1988-09-01), Mano et al.
patent: 5184324 (1993-02-01), Ohta

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