Method of metal silicide formation in integrated circuit devices

Details Method of metal silicide formation in integrated circuit devices Method of metal silicide formation in integrated circuit devices

1993-12-23

1995-03-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437178, 437179, 437201, H01L 2144, H01L 2148

Patent

active

054016770

ABSTRACT:
An improved process for the formation of high quality, high yield platinum silicides on silicon wafers uses a post sputter platinum deposition and high vacuum bake to complete the first step of silicide reaction, resulting in Pt.sub.2 Si formation before sinter. This additional process step is then followed by a 500.degree. to 900.degree. C. sinter. The use of a high vacuum bake provides easy control of O.sub.2 and H.sub.2 O impurities. The vacuum bake can be done in any high vacuum tool. The bake temperatures range from 200.degree. to 450.degree. C. at 5.times.10.sup.-6 torr, with an in-situ bake time of 3 to 5 minutes or an ex-situ bake time of 10 to 30 minutes, depending on batch size or tool. A particular advantage of the process is that it can be performed in existing tools.

REFERENCES:
patent: 4398341 (1983-08-01), Geipel, Jr. et al.
patent: 4804438 (1989-02-01), Rhodes
Wolf, Silicon Processing for the VLSI Era vol. 2 pp. 117-119 and 144-151, 1990.

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