Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-24
2002-09-10
Smith, Matthew (Department: 2829)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06449754
ABSTRACT:
The invention is related to extracting parasitic capacitance of integrated circuit interconnects and, in particular, to a method of determining the accuracy of the extraction.
BACKGROUND OF THE INVENTION
The speed at which signals propagate along an interconnection line, or interconnect, within an integrated circuit can be limited by the parasitic capacitance associated with the interconnect. In general, parasitic capacitance is the capacitance exerted on a circuit element such as an interconnect by the surrounding circuit elements. As semiconductor fabrication processes and design geometries shrink toward deep and ultra-deep submicron levels, the effect of interconnect parasitic capacitance on signal propagation becomes more pronounced. Therefore, a vital part of the integrated circuit design process is being able to accurately determine, or extract, parasitic capacitance.
One method of determining interconnect parasitic capacitance is by using a software tool called a 3-D field solver. 3-D field solvers are considered the most accurate of extraction tools because they calculate the actual lines of electromagnetic force induced by electric charges traveling through the interconnect to determine the interconnect parasitic capacitance. However, for an integrated circuit containing millions of transistors and interconnects, 3-D field solvers are extremely slow due to the enormous amount of data they have to process. In addition, preparing the input data for a 3-D field solver is a tedious and time-consuming task. Therefore, it is generally not cost-effective in terms of time and resources to use a 3-D field solver to compute the entire, full-chip interconnect parasitic capacitance of a multi-million transistor integrated circuit.
An alternative method is to estimate the full-chip interconnect parasitic capacitance using another software tool called a layout parameter extraction tool. This tool also uses a 3-D field solver, but only for creating a lookup table of parasitic capacitance models based on the particular process technology used to fabricate the circuit. The 3-D field solver calculates parasitic capacitance values based on layout parameters such as interconnect width, thickness, and proximity to other interconnects. These values are subsequently used to generate mathematical relationships or models for the parasitic capacitance based on the process technology. The models are stored in a lookup table along with the corresponding layout parameters. The tool then employs a pattern recognition algorithm to match the layout parameters of the circuit being designed with the parasitic capacitance models stored in the lookup table to generate the parasitic capacitance data for the circuit.
Tools for extracting interconnect parasitic capacitance are available to one of ordinary skill in the art such as StarRC™ from Avant! Corporation (http://www.avanticorp.com) and Fire & Ice™ from Simplex Solutions, Inc. (http://www.simplex.com).
Regardless of which tool is used, it is important to determine the accuracy of the data generated. The first step in accuracy determination is to generate a library of interconnect structures representative of the structures of the circuit being designed. Known or “golden” data for these test structures are then obtained using a 3-D field solver. The extraction tool is then applied to each test structure using the parasitic capacitance model of the extraction tool. The resulting data is compared to the known data. Finally, the extraction tool is adjusted, or calibrated, to reduce any errors to within a certain, predefined tolerance level.
In general, parasitic capacitance is determined relative to a signal path or “net,” which is one or more interconnects electrically linked together.
FIG. 1
is a schematic diagram of a section of an integrated circuit showing several nets. Blocks A
1
and A
2
represent functional circuit elements such as a memory or a control unit and are connected by a signal-carrying or “switching” net, net N. Net N in this example is the “net of interest,” that is, the net for which parasitic capacitance is to be extracted. Three other switching nets, net
, net
, and net
are on the same layer as, below, and above net N, respectively, and connect blocks B
1
to B
2
, B
3
to B
4
, and B
5
to B
6
, which blocks represent other functional circuit elements in the circuit. Although three switching nets (other than the net of interest) are shown here, there may of course be more or less than three, depending on the type of circuit. For simplicity, these switching nets will henceforth be referred to generally as net
, where i is any integer up to the number of switching nets having a capacitive influence on the net of interest. A static or non-switching net, net G, connects the grounds Vss and runs underneath net N.
Traditional extraction methods define the net capacitance C
N
of net N as:
C
N
=
C
G
+
∑
i
C
i
C
(
1
)
where C
G
is a static or non-switching capacitance between net N and net G, i is an integer number representing the switching nets other than net N, and
C
is a coupling capacitance between net N and net
. Also, an error &dgr;
N
between the extracted value of the net capacitance C
N
and a known or golden value {tilde over (C)}
N
is traditionally defined as:
δ
N
=
C
N
-
C
~
N
C
~
N
(
2
)
However, for deep and ultra-deep submicron integrated circuits, the traditional net capacitance C
N
is not directly used in signal timing analysis.
Similarly, referring still to
FIG. 1
, for crosstalk noise analysis, traditional extraction methods define a crosstalk factor K
C
representing the crosstalk between net N and the other switching nets as:
K
C
=
∑
i
C
i
C
C
G
+
∑
C
i
C
(
3
)
The crosstalk factor error &dgr;
K
in the extracted value of the crosstalk factor K
C
,like the error &dgr;
N
of equation (2), is traditionally defined as:
δ
K
=
K
C
-
K
~
C
K
~
C
(
4
)
where {tilde over (K)}
C
is a known crosstalk factor for the given circuit.
SUMMARY OF THE INVENTION
The present invention is directed to a technique that defines an error in an extracted parasitic capacitance for a net of interest as a sum of the errors in the extracted values of the individual capacitance elements which make up the total parasitic capacitance, with the error of each element being influenced by a weight factor. For purposes of signal timing analysis, the capacitance element corresponding to the error having the highest weight factor will have the biggest impact on signal propagation delay.
Similarly, the technique of the present invention defines the error in the extracted value of a crosstalk factor for the net of interest as a difference between the errors in the extracted values of the individual capacitance elements, with the error in each element being influenced by a weight factor. For purposes of crosstalk analysis, the capacitance element corresponding to the error having the highest weight factor will have the biggest impact on crosstalk.
In one embodiment, the invention is related to a method of increasing the accuracy of an interconnect parasitic capacitance extraction tool. The method includes the steps of extracting a parasitic capacitance of a net of interest with the extraction tool, calculating the error between the extracted parasitic capacitance and a known parasitic capacitance, applying a weight factor to the error to produce a weighted error, and selectively adjusting the extraction tool based on the weighted error.
In one embodiment, the invention is related to a computer for extracting a parasitic capacitance of an integrated circuit interconnect. The computer includes a microprocessor and a storage medium. The storage medium stores computer-readable instructions for instructing the microprocessor to extract a parasitic capacitance of a net of interest, calculate an error between the extracted parasitic capacitance and a known parasitic capacitance, apply a weight factor to the error to produce a weighted error, and selectively adjust an ext
MacDonald John F.
Xie Weize
You Eileen H.
Dinh Paul
Rosenthal & Osha L.L.P.
Smith Matthew
Sun Microsystems Inc.
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